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eDMA_FifoGetStartFromShadowDMA_RecFifoGetStartByIdDMA_InjFifoGetStartFromShadowByIdDMA_FifoUpdateFreeSpaceFromShadowDMA_FifoSetTailDMA_RecFifoSetTailByIdDMA_InjFifoSetTailByIdDMA_InjFifoIncrementTailDMA_InjFifoIncrementTailByIdDMA_FifoSetHeadDMA_RecFifoSetHeadByIdDMA_RecFifoIncrementHeadDMA_RecFifoIncrementHeadByIdDMA_InjFifoSetHeadDMA_InjFifoSetHeadByIdDMA_FifoGetTailDMA_RecFifoGetTailByIdDMA_InjFifoGetTailByIdDMA_FifoGetHeadDMA_RecFifoGetHeadByIdDMA_InjFifoGetHeadByIdDMA_FifoGetFreeSpaceDMA_RecFifoGetFreeSpaceByIdDMA_InjFifoGetFreeSpaceByIdDMA_InjFifoHasSpaceDMA_InjFifoHasSpaceByIdDMA_InjFifoIsDescriptorDoneDMA_InjFifoIsDescriptorDoneByIdDMA_CounterGetGlobalIdDMA_CounterGetGroupNumDMA_CounterGetGroupStatusDMA_CounterGroupClearHitZeroDMA_CounterGetEnabledDMA_CounterSetDisableDMA_CounterSetEnableDMA_CounterClearHitZeroByIdDMA_CounterGetEnabledByIdDMA_CounterSetDisableByIdDMA_CounterSetEnableByIdDMA_CounterGetMaxDMA_CounterGetMaxByIdDMA_CounterGetBaseDMA_CounterGetBaseByIdDMA_CounterGetMaxHwDMA_CounterGetBaseHwDMA_CounterGetValueHwDMA_CounterGetValueNoMsyncDMA_CounterGetValueDMA_CounterGetValueByIdDMA_CounterSetValueBaseMaxHwDMA_CounterSetValueBaseHwDMA_CounterDecrementHwDMA_CounterDecrementDMA_CounterDecrementByIdDMA_CounterIncrementHwDMA_CounterIncrementDMA_CounterIncrementByIdDMA_CounterSetBaseHwDMA_CounterSetValueHwDMA_CounterSetValueDMA_CounterSetValueByIdKernel_VaTo4bitShiftedPaDMA_CounterGetAppSegmentsDMA_CounterGetMinMaxVaDMA_InjFifoInjectDescriptorsDMA_InjFifoInjectDescriptorsByIdDMA_InjFifoInjectDescriptorDMA_InjFifoInjectDescriptorByIdDMA_InjFifoInjectDescriptorNoSpaceCheckDMA_InjFifoInjectDescriptorNoSpaceCheckByIdDMA_InjFifoGroupAllocateDMA_CounterGetOffsetFromBaseDMA_CounterGetOffsetFromBaseByIdDMA_CounterSetValueBaseMaxDMA_CounterSetValueBaseMaxByIdDMA_CounterSetValueBaseDMA_CounterSetValueBaseByIdDMA_CounterSetMaxDMA_CounterSetMaxByIdDMA_CounterSetBaseDMA_CounterSetBaseByIdDMA_CounterGroupAllocatepersist_openpthread_create_CommThread_npDMA_CounterGetHitZeroByIdDMA_CounterGetHitZeroDMA_CounterGetAllHitZeroGlobInt_InitializeUPC_Init_Hardware_CountersUPC_ActiveBGP_UPC_Check_ActiveUPC_AllocateUPC_Check_Event_Id_ValueUPC_DeallocateUPC_Get_CounterIdUPC_Active_EventUPC_Check_Monitored_Event_IdBGP_UPC_Check_Active_EventUPC_Init_Config_InternalUPC_Get_UserModeUPC_Increment_Counter_State_GenNumUPC_Increment_Start_Stop_GenNumUPC_Reset_StateUPC_Try_AllocateUPC_Zero_CtrsUPC_Init_ConfigUPC_Read_CtrUPC_Read_UnitUPC_Check_User_Mode_ValueUPC_Check_Event_Edge_ValueBGP_UPC_Zero_Counter_ValuesBGP_UPC_StartBGP_UPC_Read_Counter_ValueBGP_UPC_Read_CounterBGP_UPC_Initialize_Counter_ConfigUPC_Read_Counter_ValuesBGP_UPC_Read_Counter_ValuesBGP_UPC_Read_CountersBGP_UPC_Get_Event_NameBGP_UPC_Get_Event_DescriptionAllocate_UPC_MutexAllocate_UPC_CounterUPC_Allocate_Global_State_VariablesBGP_UPC_InitializeBGP_UPC_Get_Counter_ModeBGP_UPC_Get_Counter_Threshold_ValueBGP_UPC_Print_Counter_ValueBGP_UPC_Print_Counter_ValuesBGP_UPC_Read_Counter_ConfigBGP_UPC_Monitor_EventBGP_UPC_Set_Counter_ValueBGP_UPC_Set_Counter_Threshold_ValueBGP_UPC_Get_Counter_State_GenNumBGP_UPC_Get_Start_Stop_GenNumBGP_UPC_Print_ConfigBGP_UPC_StopBGP_UPC_Zero_Counter_ValueUPC_DO_NOT_ALLOW_TIME_EVENTSUPC_ALLOW_TIME_EVENTSUPC_NOT_MONITOREDUPC_MONITOREDUPC_SHAREDUPC_EXCLUSIVE// 122 ` DMA_Descriptors.cna.o/ spi_collective.cna.o/ DMA_RecFifo.cna.o/ DMA_InjFifo.cna.o/ DMA_Counter.cna.o/ bgp_cna_SPI.cna.o/ /0 1202797743 272974438786100644 14780 ` ELFX4( !P9`9!8}#Kx}d[xD|hx=@!9j +! +! +|8 |8!N !|<|y}TSx|3x|+x|#x !$A(a,};Kx0|;x4}Cx8D!LPAXAU@+A+A+?A+A,= ;/AD@@,@@@ @@T9`WdS{W*02+Sd!T}J8?__ A /A8T~/T~Aȁ+P l$Axai?SiE?8`R@.!H?D| !$A(a,048<8!@N +@,<`<<8c@888HHKUi?K\<`<<8c888t8H<`<<8c88t8H<`<<8c(88t8H<`<<8cH88t8H<`<<8cP88t8H<`<<8cd88t8H<`<<8ct88t8H<`<<8c88t8H<`<<8c88t8H<`<<8c88t8H<`<<8c88`8|H!|X|~y<}Cx@|;x!D}YSxAH}:KxaL|3xP|+xT|#x\dA+A+?A+A= ;/A9;+A\8| H0q @t<`}+9@q A4 x@@\<`<<8c888H<`<<8c@888HHKlx@A,hxalhx xx9 A !aH8`dd<@!D|AHaLPTX\8!`N x@@|<`<<8cD888H<`<<8c888H<`<<8cP888H<`<<8cd888H<`<<8ct888H<`<<8cd888H!|<|y|#x|3x|+x !$}YSxA(a,};Kx0}Cx4|;x8DLPAXAT@+A+A+?A +A8+?AP= ;/AH@@P@@d @@x9`WdS{Wj02+Sd!H}J8?__ A /A@8T~/T~Á?+P l$a Axa W 02SE})?8`TD| !$A(a,048<8!@N +@,<`<<8c@888HHKTK\<`<<8c8888H<`<<8c888H<`<<8c(888H<`<<8cH888H<`<<8cP888H<`<<8cd888H<`<<8c888H<`<<8c888H<`<<8c888H<`<<8c888H<`<<8c888H<`<<8c88`8|H!|X|~y<}Cx@}XSx!D}9KxAH|+xaL|;xP|3xT|#x\dA+A+?A+A+?A= ;/A9:+A\8| H0q @t<`}+9@q A4 x@@\<`<<8c88 8,H<`<<8c@88 80HHKlx@ALhGxalxjxx9! aH8`dd<@!D|AHaLPTX\8!`N x@@|<`<<8cD88 8 H<`<<8c88 8H<`<<8cP88 8H<`<<8cd88 8H<`<<8c88 8H<`<<8c88 8H<`<<8cd88 8&H!||ly}CSx|3x$}&KxA+A+?A+AT02T{+9 }JBPd8,,L9@ l,,l A /A8T~/T ~A8 8`,P@.QIl$ ,$8! |N <`<<8c888D8lH<`<<8c88D8WH<`<<8cP88D8XH<`<<8cd88D8YH<`<<8ct88D8ZH<`<<8c88`8|H!}&|<|y|#x|3x |+x!$}YSxA(}:Kxa,0}Cx4|;x8DaLPAT@*A+A+?A+A+A= ;/A(@@@@( @@<9`WdS`{9 S`dWJ02|xHQ'l$+}J`9 ? _A` }CxWi(4SE})8?8`D|}  !$A(a,048<8!@N @,<`<<8c@888HHK؁UKT<`<<8c888H<`<<8c(888H<`<<8cH888H<`<<8cP888H<`<<8cd888H<`<<8c888H<`<<8c888H<`<<8c888H<`<<8c888H<`<<8c888H!|,} CxA+A+?A+A+AT{9PdT02Q l$T(4|Z}J*9`a)c#8 cC 8!cc8`|N <`<<8c888H<`<<8cP888H<`<<8cd888H<`<<8c888 H<`<<8c888!H!|,}LSx}?Kx$A+A+?A+A(+?A@T02T{+9 }J*Pd8##C9@c## A /A8 T~/T ~A<T02})B#Q@l$`8`$8! |N <`<<8c8888H<`<<8c888H<`<<8cP888H<`<<8cd888H<`<<8c888H<`<<8c888H<`<<8c88`8|H!||jyA+A+?AT02+9 }k*8*****9  j A /A8T~/T ~A( 8`Q l$` 8!|N <`<<8c8888H<`<<8c888H<`<<8cP888H<`<<8cd888H<`<<8c88`8|Hdesc != ((void *)0)DMA_Descriptors.c(hints & 0x0000003F) == hintsvc <= 3inj_ctr_grp_id < 4inj_ctr_id < 64recv_fifo_grp_id < 4x < personality_info.xNodesy < personality_info.yNodesz < personality_info.zNodesmsg_len > 0/bgsys/drivers/DRV060_2008-080212P/ppc/arch/include/spi/DMA_Descriptors.hc!=00dest <= personality_info.xNodesdest <= personality_info.yNodesdest <= personality_info.zNodesrecv_ctr_grp_id < 4recv_ctr_id < 64recv_inj_fifo_grp_id < 4recv_inj_fifo_id < 32DMA_TorusMemFifoBcastDescriptorDMA_TorusDirectPutBcastDescriptorDMA_LocalMemFifoDescriptorDMA_PacketChunksDMA_TorusMemFifoDescriptorDMA_SetVcDMA_LocalRemoteGetDescriptorDMA_TorusRemoteGetDescriptorDMA_LocalPrefetchOnlyDescriptorDMA_LocalDirectPutDescriptorDMA_TorusDirectPutDescriptorGCC: (GNU) 4.1.2 (BGP).symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.4.rodata.comment.note.GNU-stack 4l  &, 12@<HQa8  8h $ =tV`o  "D 7pNp`iwp@  d 0(D+lH(DDMA_Descriptors.cpersonality_info__PRETTY_FUNCTION__.5030__PRETTY_FUNCTION__.7704__PRETTY_FUNCTION__.5083__PRETTY_FUNCTION__.7828__PRETTY_FUNCTION__.7528__PRETTY_FUNCTION__.7782__PRETTY_FUNCTION__.7750__PRETTY_FUNCTION__.7632__PRETTY_FUNCTION__.7673__PRETTY_FUNCTION__.7577__PRETTY_FUNCTION__.7605DMA_GetPersonalityInfoDMA_TorusMemFifoDescriptor__assert_failDMA_TorusMemFifoBcastDescriptorDMA_TorusDirectPutDescriptorDMA_TorusDirectPutBcastDescriptorDMA_LocalMemFifoDescriptorDMA_TorusRemoteGetDescriptorDMA_LocalRemoteGetDescriptorDMA_LocalDirectPutDescriptorDMA_LocalPrefetchOnlyDescriptor&.b >@BFJ@NRX \ r8vzt~8t tt (t(t HtHt PtPt  dtd"&t, 2t6:t>tBFtL RVZt^bftl rvzt~t tt `` >BF @@  ( DD  PP dd t t "d&*.d26< @"&@*.4 8 N8RVZ8^bh nrvz~ (( HH PP dd        " ( . 2 6 : > B H N R V Z ^ b h n r v z ~            `   `  B F J        @   @     , D   D         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HW:|xH99|{x|H.T 6}_*@A|.|iP@ATH|`y| A99`H99kB@}_Z*H@A| .|iP@@99}I. }>9)@A$A= 9)}= 0) && (fifo_id < (8 + 1))( (uint32_t) va_end - (uint32_t)va_start ) >= (512 + (256 * 32))fg_ptr->status_ptr != ((void *)0)(word == 0) || (word == 1)/bgsys/drivers/DRV060_2008-080212P/ppc/arch/include/spi/DMA_InjFifo.hfifo_id >= 0 && fifo_id < 32(fg_ptr->permissions & ((1<<(31-(fifo_id))))) != 0va_start < va_endva_start <= va_head((uint32_t) va_head) <= ( ((uint32_t) va_end) - 2*16)( ( (uint32_t) va_start) & 0xFFFFFFE0) == (uint32_t) va_start( ( (uint32_t) va_end ) & 0xFFFFFFE0) == (uint32_t) va_end( (unsigned)va_end - (unsigned)va_start ) >= ( (32 + 2) * 16 )(deact & fg_ptr->permissions) == deact(fifo_id >= 0) && (fifo_id < 32)( fg_ptr->permissions & ((1<<(31-(fifo_id)))) ) != 0(act & fg_ptr->permissions) == act(clr & fg_ptr->permissions) == clrf_ptr != ((void *)0)f_ptr->occupiedSize >= 2desc != ((void *)0)/bgsys/drivers/DRV060_2008-080212P/ppc/arch/include/spi/DMA_Descriptors.hmsg_len > 0skip <=1packet_chunks >=1packet_chunks <=80fifo_hw_ptr != ((void *)0)/bgsys/drivers/DRV060_2008-080212P/ppc/arch/include/spi/DMA_Fifo.hf_ptr->fifo_hw_ptr != ((void *)0)va_tail >= f_ptr->va_start && va_tail < f_ptr->va_end(incr & 0x1) == 0va_head >= f_ptr->va_start && va_head < f_ptr->va_endread_head == 1 || read_head == 0read_tail == 1 || read_tail == 0( cg_ptr != ((void *)0) ) && ( counter_id >= 0 ) && ( counter_id < 64 )/bgsys/drivers/DRV060_2008-080212P/ppc/arch/include/spi/DMA_Counter.hcg_ptr != ((void *)0)cg_ptr->status_ptr != 0( ( reg == 0 ) || ( reg == 1 ) )counterBits == (counterBits & cg_ptr->permissions[reg])( ( cg_ptr != ((void *)0) ) && ( ( reg == 0 ) || ( reg == 1 ) ) )(counter_id >= 0) && (counter_id < 64)(cg_ptr->permissions[((counter_id)>>5)] & ((1<<(31-(((counter_id) & 0x0000001F)))))) != 0c_sw != ((void *)0)c_hw != ((void *)0)pa_max >= pa_basepPA != ((void *)0)coreNum <= 4num_desc > 0desc[i] != ((void *)0)va != ((void *)0)DMA_CounterGetOffsetFromBase: Buffer 0x%08x of length %d is out of bounds. Check length. i < numAppSegments/dev/persist/( cg_ptr != ((void *)0) ) && ( word0 != ((void *)0) ) && ( word1 != ((void *)0) )DMA_RecFifoSetClearThresholdCrossedByIdDMA_RecFifoGetThresholdCrossedByIdDMA_RecFifoGetAvailableByIdDMA_RecFifoGetNotEmptyByIdDMA_RecFifoIncrementHeadByIdDMA_RecFifoSetTailByIdDMA_RecFifoSetHeadByIdDMA_RecFifoGetFreeSpaceByIdDMA_RecFifoGetSizeByIdDMA_RecFifoGetEndByIdDMA_RecFifoGetTailByIdDMA_RecFifoGetHeadByIdDMA_RecFifoGetStartByIdDMA_RecFifoInitByIdDMA_RecFifoSetClearThresholdCrossedDMA_RecFifoGetThresholdCrossedDMA_RecFifoGetAvailableDMA_RecFifoGetNotEmptyDMA_RecFifoIncrementHeadDMA_InjFifoSetDeactivateByIdDMA_InjFifoSetActivateByIdDMA_InjFifoGetActivatedByIdDMA_InjFifoSetClearThresholdCrossedByIdDMA_InjFifoGetThresholdCrossedByIdDMA_InjFifoGetAvailableByIdDMA_InjFifoGetNotEmptyByIdDMA_InjFifoInjectDescriptorsByIdDMA_InjFifoInjectDescriptorByIdDMA_InjFifoInjectDescriptorNoSpaceCheckByIdDMA_InjFifoHasSpaceByIdDMA_InjFifoFreeDescriptorStorageReservationByIdDMA_InjFifoReserveDescriptorStorageByIdDMA_InjFifoIsDescriptorDoneByIdDMA_InjFifoGetDescriptorCountByIdDMA_InjFifoIncrementTailByIdDMA_InjFifoSetTailByIdDMA_InjFifoSetHeadByIdDMA_InjFifoGetFreeSpaceByIdDMA_InjFifoGetSizeByIdDMA_InjFifoGetEndByIdDMA_InjFifoGetTailByIdDMA_InjFifoGetHeadByIdDMA_InjFifoGetStartFromShadowByIdDMA_InjFifoInitByIdDMA_InjFifoSetDeactivateDMA_InjFifoSetActivateDMA_InjFifoGetActivatedDMA_InjFifoSetClearThresholdCrossedDMA_InjFifoGetThresholdCrossedDMA_InjFifoGetAvailableDMA_InjFifoGetNotEmptyDMA_InjFifoGetGroupNumDMA_InjFifoInjectDescriptorsDMA_InjFifoInjectDescriptorDMA_InjFifoInjectDescriptorNoSpaceCheckDMA_InjFifoHasSpaceDMA_InjFifoFreeDescriptorStorageReservationDMA_InjFifoReserveDescriptorStorageDMA_InjFifoIsDescriptorDoneDMA_InjFifoGetDescriptorCountDMA_InjFifoIncrementTailDMA_InjFifoSetHeadDMA_ZeroOutDescriptorDMA_PacketChunksDMA_SetInjCsumDMA_SetMessageLengthDMA_SetChunksDMA_SetVcDMA_SetHintsDMA_FifoGetEndPaDMA_FifoGetTailPaDMA_FifoGetHeadPaDMA_FifoGetStartPaDMA_FifoSetEndPaDMA_FifoSetTailPaDMA_FifoSetHeadPaDMA_FifoSetStartPaDMA_FifoSetTailDMA_FifoSetHeadDMA_FifoGetFreeSpaceDMA_FifoGetFreeSpaceNoUpdateCalculationDMA_FifoGetSizeDMA_FifoGetEndFromShadowDMA_FifoGetTailFromShadowDMA_FifoGetTailNoFreeSpaceUpdateDMA_FifoGetTailDMA_FifoGetHeadNoFreeSpaceUpdateDMA_FifoGetHeadDMA_FifoGetStartFromShadowDMA_FifoUpdateFreeSpaceFromShadowDMA_CounterGetGlobalIdDMA_CounterGetGroupNumDMA_CounterGetGroupStatusDMA_CounterGroupClearHitZeroDMA_CounterGetAllHitZeroDMA_CounterGetHitZeroDMA_CounterGetEnabledDMA_CounterSetDisableDMA_CounterSetEnableDMA_CounterClearHitZeroByIdDMA_CounterGetHitZeroByIdDMA_CounterGetEnabledByIdDMA_CounterSetDisableByIdDMA_CounterSetEnableByIdDMA_CounterSetValueBaseMaxByIdDMA_CounterSetValueBaseByIdDMA_CounterGetMaxByIdDMA_CounterGetOffsetFromBaseByIdDMA_CounterGetBaseByIdDMA_CounterGetValueByIdDMA_CounterSetMaxByIdDMA_CounterDecrementByIdDMA_CounterIncrementByIdDMA_CounterSetBaseByIdDMA_CounterSetValueByIdDMA_CounterGetOffsetFromBaseDMA_CounterGetMaxDMA_CounterGetBaseDMA_CounterGetValueNoMsyncDMA_CounterGetValueDMA_CounterSetValueBaseMaxDMA_CounterSetValueBaseDMA_CounterSetMaxDMA_CounterDecrementDMA_CounterIncrementDMA_CounterSetBaseDMA_CounterSetValueDMA_CounterGetMaxHwDMA_CounterGetBaseHwDMA_CounterGetValueHwDMA_CounterSetValueBaseMaxHwDMA_CounterSetValueBaseHwDMA_CounterDecrementHwDMA_CounterIncrementHwDMA_CounterSetBaseHwDMA_CounterSetValueHwKernel_VaTo4bitShiftedPaDMA_CounterGetAppSegmentsGCC: (GNU) 4.1.2 (BGP).symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.4.rodata.sbss.comment.note.GNU-stack 4uPq  &u4,u8X12u8 @~DHNW,,g  $+7(B@MXbmwlXh|$((#-LF_hx ,,DH'\$@d(Yr#`,!p0:S"l4HXp  4Mf(t(.xG$`(y! ! L(PA"Z h"s<, L ";TmD   <8\5N\gLX       / , H D a \ z t    H <  \ ) x B @ [ T t l p      #  <  U  n     ,    < 6 O! h   $( ,, ( T!    0  I  b  {       4(4 C@WPm`h`\$lL`Tl" 24$AX$Q|4nd4,H4|T 4 O Tf Tz L4       * 0B 0X LTp   8,@$dhh,<Wr048(`$$$-Ep4]$~ *@ a |(,048 DT `$%2$IX] ,oL@ /PGcz` < !|)"E"i#X#|$x%,|%&\|&9'HP'x|(L)L)L*h*h`*|"+DH7+E,0O,P\-,Hm-tH-H.H.LL.L.L/0L/|H/t$08|;0R1htv12t3|344t454?5tZ64|r67d889X: ; *;:<Q=j=>LD>?H?|@`AA|B,-B<BD^DzE\EFGpH$`HHH*IGJ\]JsKLMNOPHPQH,QCRHWRHlS0HSxHSPTTxULL UL UP ,V4 EVH \WDP qW X\H XH XP Y< Zx Z|h!!/Z!F[H!c_4!_!a!b!d"eT "-"T"q"ftT""""h#i#5#Fjp#ek@#}k#l#mX#n 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N4 N:HN>NB NFHNJNN NT NZ@N^Nb Nf@NjNn Nt Nz`N~N N`NN N OOO OO"O& O, O2HO6O: O>HOBOF OL OR@OVOZ O^@ObOf Ol Or`OvOz O~`OO O P PP PPP P$ P*HP.P2 P6HP:P> PD PJ@PNPR PV@PZP^ Pd Pj`PnPr Pv`PzP~ P PPP HPPP HP Q0R Q6Q:Q> <QBQFQJ <QP QVHQZQ^ <QbHQfQj <Qp Qv@QzQ~ <Q@QQ <Q QQQ \QQQ \Q R<T RBRFRJ xRNRRRV xR\ RbHRfRj xRnHRrRv xR| R@RR xR@RR xR RRR @RRR @R SSS TSS"S& TS, SZS^Sb lSfSjSn lSt SX SSS pSSS pS SX SSS STT T TpZ TvTzT~ TTT T THTT THTT T T@TT T@TT T UUU UUU" U( U.U2U6 U:U>UB UH UzU~U UUU U UUU UUU U U^ VVV V"V&V* V0 V_ VVV VVV V VHVV VHVV V V@VV V@VV V W&W*W. W2W6W: W@ W\a WvWzW~ WWW W Wb WXX X XX X XHX"X& X*HX.X2 X8 X>@XBXF XJ@XNXR XX XXX XXX X XXXXXXX Ye YY"Y& ,Y*Y.Y2 ,Y8 Yf YYY YYY Y YHYY YHYY Y Y@YY Y@YY Z Z$ Z^ZbZf ZjZnZr Zx Z ZjZjZZZ<ZZZ<Z [ [i [ \D@ \T( \`+ \l% ]@ ^H2 ^( ^+ ^% ^ ^ ^^ ^ ^^ ^^ ^^^ ^^ ^^ ^__ _ _ __ __"_& _*_0 _l __ ___ __ __ ___ __ __ ___ __ ` @ `<( aL2 ax@ a( aa aaa aa aa aaa aa bLn bRbV bZ b^bb bf bl brbv bz b~b b b bb b bb b b b( c2 d( d<2 d^db df$djdn dr$dx d~d d$dd d$d dp dd d,ee e ,e ee e,e"e& e*,e0 e6e: e>,eBeF eJ,eP e esesetetf fsflu fwfi f fwg gVwgzxg~xhhh (hh"h& (h, h2h6h: (h>hBhF (hL hR$hVhZ (h^$hbhf (hl hrhvhz (h~hh (h h8h8hy hdhh (hdhh (h i4v i:i>iB TiFiJiN TiT iZHi^ib TifHijin Tit iz@i~i Ti@ii Ti ih ih j\ j<| jRjVjZ j^jbjf jl j{ jjj jjj j kHkk  kHkk k k"@k&k* k.@k2k6 k< kph k] k| kkk kkk k lL~ lRlVlZ l^lblf ll lrHlvlz l~Hll l l@ll l@ll l lh m m$| m:m>mB mFmJmN mT m mmm mmm m mHmm mHmm m n@nn  n@nn n nHh n\d n| nnn nnn n o oo"o& o*o.o2 o8 o>HoBoF oJHoNoR oX o^@obof oj@onor ox ojojp p| p p ppqq4 qH q rRrVrZ r^rbrf rl rrHrvrz r~Hrr r r@rr r@rr r r`rr r`rr r rrr rrs s sn`srsv sz`s~s s ttt  ttt t tN`tRtV tZ`t^tb th UPC.cna.o/ 1202797748 272974438786100644 399180 ` ELFx4( 8!| =`ak889 &+|9kB8! N |= a)iTcN H= i 9k| /@|N +@ 8`N +A`+@(+A+@+[@8+A/@$/Ad+AL/AT/AL8`N +AD+@+A+@8+AlK/A /@8`N +A<+@|84+A4Kl+A(+@\8"+AKL/@K@8_+AK0= i | |N Tc>N !|||x$|= a)HTi8=)| Tk= l})\0|c|H8= Tc9)|0||H.WT||x$|c4Tc~8! |N !|/A(H/8`@8`8!|N H/8`@K!|<88|x$H/A$8! |N $x8! |H!}&|/!4TA8|#x0a<@DHLT,A|yx/AP/A4/8;A,W#@.;;@|x8H8;W)@.}?Kx;l= 9).}kJT;H\xHTj8=J| |kWi)+KDa,04|8<8!@N 0@@= =@a)?}P|I1}e;`gY}<`xxixx8cL1HDa,04|8<8!@N |= a) p @|= a) T/@| B}lB}-BH}*Kx@<9$i=`IK`| = ip|x| |x| BB}-BH}>Kx@= 9) }}e8}H`}'Y&FK!|8`;$HxH/;@$8! |N !||ex8+<`8c8@L1H8|x8!|N !|+ |ex8|0<`p 8c A 8A|x8!|N L1H8|x8!|N !|$HH</<`8t8c8@4H= i@|H$x8! |N L1H;HKؔ!||x$H|~xH/@/A 8<| =@= aJ9)9d89 9J| 9k 9)B= 8i` |= ip || B|B}-BH}%Kx@9$H|x|= a) ` |/@DH$x8! |N /@p= i0|/AĀ$x8! |N = =`9) +`|= ip |<K <`<8c8L1H;/@KH!= |,;$x|#x8(|~x4Aa H|`yA4|x|p4Aa |$(,8!0N x8xH|`y@+AHHH|zxxH|x|=`Ti8ak=) |/IA/Ad;H/?A8`?HH8W8A})4ia| $(,8!0N W<|\0}@8U)|L0U T?|Z/@/@9>i | [y@t| BB}-BH};Kx@9>iKL/A| T< |;K <`x8c0xL1H8`8KTH!= |;X|#xx||x$H|}yxxA($x|8! N H|}y@HHx/<`8c|@@xxHH|}xH$x|8! N L1H;HKh!}&|4|+xA(|zx0|3x<|#xD !$a,8HH/A/@|= a) p At= i0| H/|~xA.W@.H; ;`A+pALCx;/9/@= =`|gxW$<8;x9<`;`;@4U 8=)| U |k\0} @U)|X8|L0T"A|Bl}>./A%E'G9888BAh@HDx !$|A(} a,048<8!@N |Bl}>./A(%9E&@FDK|gKp9f@DK`;KH= i0| H/|~x@h|= .a); ;`T@\8+|pA=`= =` <= I 8 88z8Z_xH= 9)8`iz04K쑟K|= a) T/@x=@9*i | [y@`| B} B}-BH}'Kx@9* K8/A|= a) T< |H8`HK;K!|/+?At+@H8A8!|H<`<8c08L1H8`8!|N <`<8c88@L1H8`K<`<8c8L1H8`K!|/+At+@H8A8!|H<`<8c08@L1H8`8!|N <`<8c8@8L1H8`K<`<8c8@L1H8`K!| |+x<a$|#x8X8|}x,4lH= 9)|yJx8ex@H4xa $|,8!0N !| |+x<a$|#x8p8|}x,4lH= 9)|yJx8Aex@H4xa $|,8!0N !|T 6=,|jx$+`|x}cx8,/A8 AHAD8}#Kx|;x}ESx}CxD|kx/ A/@$8! |N 9`,<`8c}e[x}FSx9)}$Kx,L1H8`H<`8cH8`H!|T 6=,|jx$+`|x}cx8,/A8 AHAD8}#Kx|;x}ESx}CxD|kx/ A/@$8! |N 9`,<`8c}e[x}FSx9)}$Kx,L1H8`H<`8c(H8`H! |9 !9aAȓa̓Гԓؓܐ8}c[x}$KxD|jx<ha= U iA\<pAP=8R9(9`8M9@x8-i9`N 8Ji I IIIII I }EBUJ= =ޭa;ITƾ?=`= 9a 9! AaA8Cxdx}ESxx}'Kx}h[xD|yx;8Cxdx}ESxx}'Kx}h[xD|lx;8Cxdx}ESxx}'Kx}h[xD|~x;x8Cxdx}ESxx}'Kx}h[xD|~x/x@䃿;/@ ;/@ ;/@ ;<`x8c 8H<`88c0H<`88c@H<`88cPH<`88c`H<`88cpH!ăAȃa|Ѓԃ؃8!N K(U O><`8R/89 -8MUƾ'U o>UwU>A<9$`| }kH}JHgG= 9D`a)}H}&HUU) i |P|(P|P}k0P||P9#89@- 9`N8Ji I IKD8x<Kt!|$?/A$8! |N HH8| = =`9)9k89 9) 9kBH8$8! |N |= a)iTcN !|8?;tx$||xH|`yx8xA4|x|p$xx|8! N H,A4$|x|~pxx|8! N HxHTi8=)|iTj<Th8|T0|c}k8Tc}k0= q`9)}J;;@ HK@h= a)=@PIHK!= }&|(;,x|#x8 $|}x!Aa4H||yA<4x!A|a} $(,8!0N x8xH||y@+APHH/.A; xHTi8|x=)|i|=@T`aJ= })0 |`}kH8T}k0UUk}kBU~@.@/?@ /A/@8}W8l}k= 9)}J<`x98cL1HH4x!A|a} $(,8!0N H?KtA|= a) T< |; K8`HKH<`x8c0xL1H;K@9=i | [y@ | BlB}-BH}:Kx@9=IiK!}&|+\|x048<@!DAHaLPTXd,AHH/.A H;/|xA,T}@.; ;@@A/@<`.8c?H<<`88c\>L1H= <`8c|>W9L1H= <`8c;v?L1H= <`8cL1H<`x8cL1H<`8c;H<`8cpH9@Hl/@:|KyA8Z}k9k8x:a L1H9@/;Z;;;AhW88=)@0| W~L0Uk|H8|\0T|T@.|`l}+./A/A@KT/A959T}lIi8=k}k<`9kj8c Gxhxxx||a L1H<`8cTHH8`d,04|8} <@!DAHaLPTX\8!`N <`8c0HK94i |[y@d| BB}-BH};Kx@/94iA@8`HK4A|= a) T< |H;/|x@|= ;a);@ TAH>K<`<8c08xL1H8`Kܔ!= |$;ȓa|+x,x|#x8 ||x(4H|~yA,4xa $|(,8!0N x8xH|~y@/AL+G@$H= =` = =`I x_ HTi8|{x=)|Tk<|i|\0U)8L0W>W:?<88 8H8s<@@9 9@?@_DH4xa $|(,8!0N = Wk89)=@}kJ= a) }P}gI@DHK<`x8c8HL1H;Kt<`x8c;L1HKX!= |,;(x|#x8$|}x4H,A 4$(,|8!0N x8xH,@xxH,@HH/@H|= W~a) T(@/xAxHTj8=J| WϼTg|k<})x|<0Uk}x})X0|Kx ||*<|>0} x |=`Tc89k8}cZ9|) x =C9J ȩت|=`= KP9)|cJ8 |H|}xHxK}l= 9)}kJK <`x8ctL1HH8`Kh<`x8c0L1HH8`KH!= |8 ;(|+xx$,|}x4|3xH,A$4 $(|,8!0N x8xH,@HH/@0xHTi8=)|iTj<|i|T0U)}k8}kL0q`Ad=@Tc89*=`}#Jak= }`|YA8A<`xxx8c @L1HH8`K Tc8=@9*|+ x}#J=9}_8}>1+K|= 9)}#JH|}xH4x $(|,8!0N @AKL<`x8c L1HH8`Kp!= |8a,;i 8|+xex04|}x<|3xDH||yA,Dxa,04|8<8!@N x8exH||y@HH/@DxHyAX= Td89)}$JiXAA<`dxxx}g[x}cx8c ;L1HHKPTi8=)|ITk<|^0}@x |HDxa,04|8<8!@N `@@x= =@a)}P|I|@|9=`9k|) x}dZ=D9J |Tk8=k|+Tj<|V0})x+|HKT<`dx8c0;L1HHKT!|$H= i@|H$x|8! N !|$H= i0|H$x|8! N !|!Aa $4H= i0|= Ki@|+H= |xxi`| = ip|x|<`k8c H<<`88c L1H= <`8c L1H= <`8c 8L1H= <`8c XL1H= <`8c xL1H<`<`8c L1H<`<`8c L1H<= `a)<`8c L1H<`Dx8c ,L1H<`$x8c PL1H<`x8c tL1H<`xex8c ?@?`L1HcZc{;? x;Ex8hx8y ;ZL1H;{/;@<`8c H4!|Aa $8!0H!|$HH/@0= i0|H$x|8! N H|x|= a) T< |HH$x8! |N != |8,; Dx$(|~x4H|}yx8xA$4x($,|8!0N H|}y@HHx/x@H= Tc89)}#J|+ x=C 9J |= 9`9)9|cJ= ci@|H4(x,$|8!0N <`;8c0L1HHKBGP_UPC_Check_Active_EventUPC_Read_Ctr: Condition: Start counter value was less than hardware counter value, pCounterId=%d, xCounterValue=%lld, UPC_StartValues[pCounterId]=%lld, Calculated UPC_CountValues[pCounterId]=%lld %s: Invalid user mode %d specified. %s: Invalid event edge 0x%2.2X specified. %s: Cannot zero counter values with an active UPC unit. BGP_UPC_Zero_Counter_Values%s: Cannot start the UPC unit and request for the counter values to be reset if the UPC unit is currently active. BGP_UPC_StartBGP_UPC_Read_Counter_Value%s: Invalid read type %d specified. BGP_UPC_Initialize_Counter_Config%s: Cannot initialize counter configuration with an active UPC unit. %s: Buffer pointer not set. BGP_UPC_Read_Counter_Values%s: Return space size must be at least %d bytes in length. BGP_UPC_Read_CountersBGP_UPC_Get_Event_NameBGP_UPC_Get_Event_DescriptionFatal: LockBox_AllocateMutex(%d) rc=%d p=%p Fatal: LockBox_AllocateMutex: No available lockboxesFatal: LockBox_AllocateCounter(%d) rc=%d p=%p Fatal: LockBox_AllocateCounter: No available lockboxes0123456789ABCDEFBGP_UPC_Get_Counter_Threshold_ValueBGP_UPC_Print_Counter_Value%20llu %3d %s BGP_UPC_Print_Counter_Values************************************* BEGIN - BGP_UPC_Print_Counter_Values ************************************* Location: %s Rank: %d Core: %d UPC_Number: %d Processes per UPC Unit: %d User Mode: %d UPC Hardware Value Start Value Calculated Value Event Id Event Name------------------ -------------------- -------------------- -------- --------------------------------------------0x%8.8X%8.8X %20llu %20llu %3d %s %18llu %20llu %20llu %3d %s All counter values are zero.************************************* END - BGP_UPC_Print_Counter_Values ************************************* BGP_UPC_Read_Counter_Config%s: Buffer size must specify at least %d bytes. BGP_UPC_Monitor_Event%s: Cannot set a counter threshold value with an active UPC unit. %s: Counter mode for new event is incompatible with current UPC counter mode. Current UPC counter mode is %d. BGP_UPC_Set_Counter_Value%s: Cannot set a counter value with an active UPC unit. %s: Cannot set a counter value that is not less than the current threshold value. The counter value to be set is %lld and the current threshold value is %lld. BGP_UPC_Set_Counter_Threshold_Value%s: Counter threshold value to set must be greater than the current counter value. The threshold value to be set is %lld and the counter value is currently %lld. ****************** BEGIN - BGP_UPC_Print_Config ****************** Location: %s Rank: %d Core: %d UPC_Number: %d Processes per UPC Unit: %d Config/Status Reg: *(%8.8X) = %8.8X Parity Error Addr: *(%8.8X) = %8.8X Threshold Reg: *(%8.8X) = %8.8X%8.8X Start/Stop GenNbr: %8.8X Ctr State GenNbr: %8.8X User Mode: %8.8X Elapsed Time: %8.8X%8.8X CFG[%2d]: *(%8.8X) = %8.8X CFG[%2d]: *(%8.8X) = %8.8X ****************** END - BGP_UPC_Print_Config ****************** BGP_UPC_Zero_Counter_ValueBGP_PU0_JPIPE_INSTRUCTIONSP0 CPU: J-pipe instructionsBGP_PU0_JPIPE_ADD_SUBP0 CPU: Add/Sub in J-pipeBGP_PU0_JPIPE_LOGICAL_OPSP0 CPU: Logical operations in J-pipeBGP_PU0_JPIPE_SHROTMKP0 CPU: J-pipe shift/rotate/mask instructionsBGP_PU0_IPIPE_INSTRUCTIONSP0 CPU: I-pipe instructionsBGP_PU0_IPIPE_MULT_DIVP0 CPU: Mult/Div in I-pipeBGP_PU0_IPIPE_ADD_SUBP0 CPU: Add/Sub in I-pipeBGP_PU0_IPIPE_LOGICAL_OPSP0 CPU: Logical operations in I-pipeBGP_PU0_IPIPE_SHROTMKP0 CPU: I-pipe shift/rotate/mask instructionsBGP_PU0_IPIPE_BRANCHESP0 CPU: BranchesBGP_PU0_IPIPE_TLB_OPSP0 CPU: TLB operationsBGP_PU0_IPIPE_PROCESS_CONTROLP0 CPU: Process controlBGP_PU0_IPIPE_OTHERP0 CPU: Other I-pipe operationsBGP_PU0_DCACHE_LINEFILLINPROGP0 CPU: Cycles for data cache LineFillInProgressBGP_PU0_ICACHE_LINEFILLINPROGP0 CPU: Cycles for inst cache LineFillInProgressBGP_PU0_DCACHE_MISSP0 CPU: Accesses to data cache which missed data cacheBGP_PU0_DCACHE_HITP0 CPU: Accesses to data cache which hit data cacheBGP_PU0_DATA_LOADSP0 CPU: Data loadsBGP_PU0_DATA_STORESP0 CPU: Data storesBGP_PU0_DCACHE_OPSP0 CPU: Data cache operationsBGP_PU0_ICACHE_MISSP0 CPU: Accesses to inst cache which missed inst cacheBGP_PU0_ICACHE_HITP0 CPU: Accesses to inst cache which hit inst cacheBGP_PU0_FPU_ADD_SUB_1P0 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU0_FPU_MULT_1P0 FPU: Mult: fmul fmulsBGP_PU0_FPU_FMA_2P0 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU0_FPU_DIV_1P0 FPU: Div: fdiv, fdivsBGP_PU0_FPU_OTHER_NON_STORAGE_OPSP0 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb1BGP_PU0_FPU_ADD_SUB_2P0 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU0_FPU_MULT_2P0 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU0_FPU_FMA_4P0 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU0_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPSP0 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU0_FPU_QUADWORD_LOADSP0 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU0_FPU_OTHER_LOADSP0 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU0_FPU_QUADWORD_STORESP0 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU0_FPU_OTHER_STORESP0 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU1_JPIPE_INSTRUCTIONSP1 CPU: J-pipe instructionsBGP_PU1_JPIPE_ADD_SUBP1 CPU: Add/Sub in J-pipeBGP_PU1_JPIPE_LOGICAL_OPSP1 CPU: Logical operations in J-pipeBGP_PU1_JPIPE_SHROTMKP1 CPU: J-pipe shift/rotate/mask instructionBGP_PU1_IPIPE_INSTRUCTIONSP1 CPU: I-pipe instructionsBGP_PU1_IPIPE_MULT_DIVP1 CPU: Mult/Div in I-pipeBGP_PU1_IPIPE_ADD_SUBP1 CPU: Add/Sub in I-pipeBGP_PU1_IPIPE_LOGICAL_OPSP1 CPU: Logical operations in I-pipeBGP_PU1_IPIPE_SHROTMKP1 CPU: I-pipe shift/rotate/mask instructionBGP_PU1_IPIPE_BRANCHESP1 CPU: BranchesBGP_PU1_IPIPE_TLB_OPSP1 CPU: TLB operationsBGP_PU1_IPIPE_PROCESS_CONTROLP1 CPU: Process controlBGP_PU1_IPIPE_OTHERP1 CPU: Other I-pipe operationsBGP_PU1_DCACHE_LINEFILLINPROGP1 CPU: Cycles for data cache LineFillInProgressBGP_PU1_ICACHE_LINEFILLINPROGP1 CPU: Cycles for inst cache LineFillInProgressBGP_PU1_DCACHE_MISSP1 CPU: Accesses to data cache which missed data cacheBGP_PU1_DCACHE_HITP1 CPU: Accesses to data cache which hit data cacheBGP_PU1_DATA_LOADSP1 CPU: Data loadsBGP_PU1_DATA_STORESP1 CPU: Data storesBGP_PU1_DCACHE_OPSP1 CPU: Data cache operationsBGP_PU1_ICACHE_MISSP1 CPU: Accesses to inst cache which missed inst cacheBGP_PU1_ICACHE_HITP1 CPU: Accesses to inst cache which hit inst cacheBGP_PU1_FPU_ADD_SUB_1P1 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU1_FPU_MULT_1P1 FPU: Mult: fmul fmulsBGP_PU1_FPU_FMA_2P1 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU1_FPU_DIV_1P1 FPU: Div: fdiv, fdivsBGP_PU1_FPU_OTHER_NON_STORAGE_OPSP1 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb2BGP_PU1_FPU_ADD_SUB_2P1 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU1_FPU_MULT_2P1 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU1_FPU_FMA_4P1 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU1_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPSP1 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU1_FPU_QUADWORD_LOADSP1 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU1_FPU_OTHER_LOADSP1 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU1_FPU_QUADWORD_STORESP1 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU1_FPU_OTHER_STORESP1 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU0_L1_INVALIDATION_REQUESTSP0 L1: Invalidation requestedBGP_PU1_L1_INVALIDATION_REQUESTSP1 L1: Invalidation requestedBGP_PU0_L2_VALID_PREFETCH_REQUESTSP0 L2: Pre-fetch request validBGP_PU0_L2_PREFETCH_HITS_IN_FILTERP0 L2: Pre-fetch hits in filterBGP_PU0_L2_PREFETCH_HITS_IN_STREAMP0 L2: Pre-fetch hits in active streamBGP_PU0_L2_CYCLES_PREFETCH_PENDINGP0 L2: Number of cycles for which L2 pre-fetch is pendingBGP_PU0_L2_PAGE_ALREADY_IN_L2P0 L2: Requested PF is already in L2BGP_PU0_L2_PREFETCH_SNOOP_HIT_SAME_COREP0 L2: Pre-fetch snoop hit from same core (write)BGP_PU0_L2_PREFETCH_SNOOP_HIT_OTHER_COREP0 L2: Pre-fetch snoop hit from other coreBGP_PU0_L2_PREFETCH_SNOOP_HIT_PLBP0 L2: Pre-fetch snoop hit PLB (write)BGP_PU0_L2_CYCLES_READ_REQUEST_PENDINGP0 L2: Number of cycles for which read request is pendingBGP_PU0_L2_READ_REQUESTSP0 L2: Read requestsBGP_PU0_L2_DEVBUS_READ_REQUESTSP0 L2: Devbus read requests (SRAM, LOCK, and UPC)BGP_PU0_L2_L3_READ_REQUESTSP0 L2: L3 read requestBGP_PU0_L2_NETBUS_READ_REQUESTSP0 L2: Netbus read requests (tree and torus)BGP_PU0_L2_BLIND_DEV_READ_REQUESTSP0 L2: Blind device read requestBGP_PU0_L2_PREFETCHABLE_REQUESTSP0 L2: Pre-fetchable requestsBGP_PU0_L2_HITP0 L2: L2 hitBGP_PU0_L2_SAME_CORE_SNOOPSP0 L2: Same core snoopsBGP_PU0_L2_OTHER_CORE_SNOOPSP0 L2: Other core snoopsBGP_PU0_L2_OTHER_DP_PU0_SNOOPSP0 L2: Other DP PU0 snoopsBGP_PU0_L2_OTHER_DP_PU1_SNOOPSP0 L2: Other DP PU1 snoopsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReserved BGP_PU0_L2_MEMORY_WRITESP0 L2: Writes to memory BGP_PU0_L2_NETWORK_WRITESP0 L2: Writes to networkBGP_PU0_L2_DEVBUS_WRITESP0 L2: Writes to devbusBGP_PU1_L2_VALID_PREFETCH_REQUESTSP1 L2: Pre-fetch request validBGP_PU1_L2_PREFETCH_HITS_IN_FILTERP1 L2: Pre-fetch hits in filterBGP_PU1_L2_PREFETCH_HITS_IN_STREAMP1 L2: Pre-fetch hits in active streamBGP_PU1_L2_CYCLES_PREFETCH_PENDINGP1 L2: Number of cycles for which L2 pre-fetch is pendingBGP_PU1_L2_PAGE_ALREADY_IN_L2P1 L2: Requested PF is already in L2BGP_PU1_L2_PREFETCH_SNOOP_HIT_SAME_COREP1 L2: Pre-fetch snoop hit from same core (write)BGP_PU1_L2_PREFETCH_SNOOP_HIT_OTHER_COREP1 L2: Pre-fetch snoop hit from other coreBGP_PU1_L2_PREFETCH_SNOOP_HIT_PLBP1 L2: Pre-fetch snoop hit PLB (write)BGP_PU1_L2_CYCLES_READ_REQUEST_PENDINGP1 L2: Number of cycles for which read request is pendingBGP_PU1_L2_READ_REQUESTSP1 L2: Read requestsBGP_PU1_L2_DEVBUS_READ_REQUESTSP1 L2: Devbus read requests (SRAM, LOCK, and UPC)BGP_PU1_L2_L3_READ_REQUESTSP1 L2: L3 read requestBGP_PU1_L2_NETBUS_READ_REQUESTSP1 L2: Netbus read requests (tree and torus)BGP_PU1_L2_BLIND_DEV_READ_REQUESTSP1 L2: Blind device read requestBGP_PU1_L2_PREFETCHABLE_REQUESTSP1 L2: Pre-fetchable requestsBGP_PU1_L2_HITP1 L2: L2 hitBGP_PU1_L2_SAME_CORE_SNOOPSP1 L2: Same core snoopsBGP_PU1_L2_OTHER_CORE_SNOOPSP1 L2: Other core snoopsBGP_PU1_L2_OTHER_DP_PU0_SNOOPSP1 L2: Other DP PU0 snoopsBGP_PU1_L2_OTHER_DP_PU1_SNOOPSP1 L2: Other DP PU1 snoopsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReserved BGP_PU1_L2_MEMORY_WRITESP1 L2: Writes to memory BGP_PU1_L2_NETWORK_WRITESP1 L2: Writes to networkBGP_PU1_L2_DEVBUS_WRITESP1 L2: Writes to devbusBGP_L3_M0_RD0_SINGLE_LINE_DELIVERED_L2L3 M0 Rd 0: Single line delivered to L2BGP_L3_M0_RD0_BURST_DELIVERED_L2L3 M0 Rd 0: Burst delivered to L2BGP_L3_M0_RD0_READ_RETURN_COLLISIONL3 M0 Rd 0: Read return collisionBGP_L3_M0_RD0_DIR0_HIT_OR_INFLIGHTL3 M0 Rd 0: dir0 hit or in flightBGP_L3_M0_RD0_DIR0_MISS_OR_LOCKDOWNL3 M0 Rd 0: dir0 miss or lock-downBGP_L3_M0_RD0_DIR1_HIT_OR_INFLIGHTL3 M0 Rd 0: dir1 hit or in flightBGP_L3_M0_RD0_DIR1_MISS_OR_LOCKDOWNL3 M0 Rd 0: dir1 miss or lock-downBGP_L3_M0_RD1_SINGLE_LINE_DELIVERED_L2L3 M0 Rd 1: Single line delivered to L2BGP_L3_M0_RD1_BURST_DELIVERED_L2L3 M0 Rd 1: Burst delivered to L2BGP_L3_M0_RD1_READ_RETURN_COLLISIONL3 M0 Rd 1: Read return collisionBGP_L3_M0_RD1_DIR0_HIT_OR_INFLIGHTL3 M0 Rd 1: dir0 hit or in flightBGP_L3_M0_RD1_DIR0_MISS_OR_LOCKDOWNL3 M0 Rd 1: dir0 miss or lock-downBGP_L3_M0_RD1_DIR1_HIT_OR_INFLIGHTL3 M0 Rd 1: dir1 hit or in flightBGP_L3_M0_RD1_DIR1_MISS_OR_LOCKDOWNL3 M0 Rd 1: dir1 miss or lock-downBGP_L3_M0_DIR0_LOOKUPSL3 M0 Dir 0: Number of lookupsBGP_L3_M0_DIR0_CYCLES_REQUESTS_NOT_TAKENL3 M0 Dir 0: Number of cycles with requests that are not takenBGP_L3_M0_DIR1_LOOKUPSL3 M0 Dir 1: Number of lookupsBGP_L3_M0_DIR1_CYCLES_REQUESTS_NOT_TAKENL3 M0 Dir 1: Number of cycles with requests that are not takenBGP_L3_M0_MH_DDR_STORESL3 M0 MH: Number of stores to DDRBGP_L3_M0_MH_DDR_FETCHESL3 M0 MH: Number of fetches from DDRBGP_L3_M1_RD0_SINGLE_LINE_DELIVERED_L2L3 M1 Rd 0: Single line delivered to L2BGP_L3_M1_RD0_BURST_DELIVERED_L2L3 M1 Rd 0: Burst delivered to L2BGP_L3_M1_RD0_READ_RETURN_COLLISIONL3 M1 Rd 0: Read return collisionBGP_L3_M1_RD0_DIR0_HIT_OR_INFLIGHTL3 M1 Rd 0: dir0 hit or in flightBGP_L3_M1_RD0_DIR0_MISS_OR_LOCKDOWNL3 M1 Rd 0: dir0 miss or lock-downBGP_L3_M1_RD0_DIR1_HIT_OR_INFLIGHTL3 M1 Rd 0: dir1 hit or in flightBGP_L3_M1_RD0_DIR1_MISS_OR_LOCKDOWNL3 M1 Rd 0: dir1 miss or lock-downBGP_L3_M1_RD1_SINGLE_LINE_DELIVERED_L2L3 M1 Rd 1: Single line delivered to L2BGP_L3_M1_RD1_BURST_DELIVERED_L2L3 M1 Rd 1: Burst delivered to L2BGP_L3_M1_RD1_READ_RETURN_COLLISIONL3 M1 Rd 1: Read return collisionBGP_L3_M1_RD1_DIR0_HIT_OR_INFLIGHTL3 M1 Rd 1: dir0 hit or in flightBGP_L3_M1_RD1_DIR0_MISS_OR_LOCKDOWNL3 M1 Rd 1: dir0 miss or lock-downBGP_L3_M1_RD1_DIR1_HIT_OR_INFLIGHTL3 M1 Rd 1: dir1 hit or in flightBGP_L3_M1_RD1_DIR1_MISS_OR_LOCKDOWNL3 M1 Rd 1: dir1 miss or lock-downBGP_L3_M1_DIR0_LOOKUPSL3 M1 Dir 0: Number of lookupsBGP_L3_M1_DIR0_CYCLES_REQUESTS_NOT_TAKENL3 M1 Dir 0: Number of cycles with requests that are not takenBGP_L3_M1_DIR1_LOOKUPSL3 M1 Dir 1: Number of lookupsBGP_L3_M1_DIR1_CYCLES_REQUESTS_NOT_TAKENL3 M1 Dir 1: Number of cycles with requests that are not takenBGP_L3_M1_MH_DDR_STORESL3 M1 MH: Number of stores to DDRBGP_L3_M1_MH_DDR_FETCHESL3 M1 MH: Number of fetches from DDRBGP_PU0_SNOOP_PORT0_REMOTE_SOURCE_REQUESTSP0 SNP: Port 0 received a snoop request from a remote sourceBGP_PU0_SNOOP_PORT1_REMOTE_SOURCE_REQUESTSP0 SNP: Port 1 received a snoop request from a remote sourceBGP_PU0_SNOOP_PORT2_REMOTE_SOURCE_REQUESTSP0 SNP: Port 2 received a snoop request from a remote sourceBGP_PU0_SNOOP_PORT3_REMOTE_SOURCE_REQUESTSP0 SNP: Port 3 received a snoop request from a remote sourceBGP_PU0_SNOOP_PORT0_REJECTED_REQUESTSP0 SNP: Port 0 snoop filter rejected a snoop requestBGP_PU0_SNOOP_PORT1_REJECTED_REQUESTSP0 SNP: Port 1 snoop filter rejected a snoop requestBGP_PU0_SNOOP_PORT2_REJECTED_REQUESTSP0 SNP: Port 2 snoop filter rejected a snoop requestBGP_PU0_SNOOP_PORT3_REJECTED_REQUESTSP0 SNP: Port 3 snoop filter rejected a snoop requestBGP_PU0_SNOOP_L1_CACHE_WRAPP0 SNP: Snoop filter detected an L1 cache wrapBGP_PU1_SNOOP_PORT0_REMOTE_SOURCE_REQUESTSP1 SNP: Port 0 received a snoop request from a remote sourceBGP_PU1_SNOOP_PORT1_REMOTE_SOURCE_REQUESTSP1 SNP: Port 1 received a snoop request from a remote sourceBGP_PU1_SNOOP_PORT2_REMOTE_SOURCE_REQUESTSP1 SNP: Port 2 received a snoop request from a remote sourceBGP_PU1_SNOOP_PORT3_REMOTE_SOURCE_REQUESTSP1 SNP: Port 3 received a snoop request from a remote sourceBGP_PU1_SNOOP_PORT0_REJECTED_REQUESTSP1 SNP: Port 0 snoop filter rejected a snoop requestBGP_PU1_SNOOP_PORT1_REJECTED_REQUESTSP1 SNP: Port 1 snoop filter rejected a snoop requestBGP_PU1_SNOOP_PORT2_REJECTED_REQUESTSP1 SNP: Port 2 snoop filter rejected a snoop requestBGP_PU1_SNOOP_PORT3_REJECTED_REQUESTSP1 SNP: Port 3 snoop filter rejected a snoop requestBGP_PU1_SNOOP_L1_CACHE_WRAPP1 SNP: Snoop filter detected an L1 cache wrapBGP_TORUS_XP_PACKETSTORUS: Number of packets sent to X+ dimensionBGP_TORUS_XP_32BCHUNKSTORUS: Number of 32B chunks sent to X+BGP_TORUS_XM_PACKETSTORUS: Number of packets sent to X-dimensionBGP_TORUS_XM_32BCHUNKSTORUS: Number of 32B chunks sent to X-BGP_TORUS_YP_PACKETSTORUS: Number of packets sent to Y+ dimensionBGP_TORUS_YP_32BCHUNKSTORUS: Number of 32B chunks sent to Y+BGP_TORUS_YM_PACKETSTORUS: Number of packets sent to Y-dimensionBGP_TORUS_YM_32BCHUNKSTORUS: Number of 32B chunks sent to Y-BGP_TORUS_ZP_PACKETSTORUS: Number of packets sent to Z+ dimensionBGP_TORUS_ZP_32BCHUNKSTORUS: Number of 32B chunks sent to Z+BGP_TORUS_ZM_PACKETSTORUS: Number of packets sent to Z-dimensionBGP_TORUS_ZM_32BCHUNKSTORUS: Number of 32B chunks sent to Z-BGP_DMA_PACKETS_INJECTEDDMA: Number of packets injectedBGP_DMA_DESCRIPTORS_READ_FROM_L3DMA: Number of descriptors read from L3BGP_DMA_FIFO_PACKETS_RECEIVEDDMA: Number of fifo packets receivedBGP_DMA_COUNTER_PACKETS_RECEIVEDDMA: Number of counter packets receivedBGP_DMA_REMOTE_GET_PACKETS_RECEIVEDDMA: Number of remote get packets receivedBGP_DMA_IDPU_READ_REQUESTS_TO_L3DMA: Number of read requests to L3 by IDPUBGP_DMA_READ_VALID_RETURNEDDMA: Number of read valid returned from L3BGP_DMA_ACKED_READ_REQUESTSDMA: Number of acknowledged read requestsBGP_DMA_CYCLES_RDPU_WRITE_ACTIVEDMA: Number of cycles RDPU wants to write to L3, independent of the write readyBGP_DMA_WRITE_REQUESTS_TO_L3DMA: Number of write requests to L3ReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedBGP_COL_AC_CH2_VC0_MATURECOL: Arbiter_core ch2_vc0_matureBGP_COL_AC_CH1_VC0_MATURECOL: Arbiter_core ch1_vc0_matureBGP_COL_AC_CH0_VC0_MATURECOL: Arbiter_core ch0_vc0_matureBGP_COL_AC_INJECT_VC0_MATURECOL: Arbiter_core inj_vc0_matureBGP_COL_AC_CH2_VC1_MATURECOL: Arbiter_core ch2_vc1_matureBGP_COL_AC_CH1_VC1_MATURECOL: Arbiter_core ch1_vc1_matureBGP_COL_AC_CH0_VC1_MATURECOL: Arbiter_core ch0_vc1_matureBGP_COL_AC_INJECT_VC1_MATURECOL: Arbiter_core inj_vc1_matureBGP_COL_AC_PENDING_REQUESTSCOL: Arbiter_core requests pendingBGP_COL_AC_WAITING_REQUESTSCOL: Arbiter_core requests waiting (ready to go)BGP_COL_AR2_PACKET_TAKENCOL: Arbiter receiver 2 packet takenBGP_COL_AR1_PACKET_TAKENCOL: Arbiter receiver 1 packet takenBGP_COL_AR0_PACKET_TAKENCOL: Arbiter receiver 0 packet takenBGP_COL_ALC_PACKET_TAKENCOL: Arbiter local client packet takenBGP_COL_AR0_VC0_DATA_PACKETS_RECEIVEDCOL: Receiver 0 vc0 data packet receivedBGP_COL_AR0_VC1_DATA_PACKETS_RECEIVEDCOL: Receiver 0 vc1 data packet receivedBGP_COL_AR1_VC0_DATA_PACKETS_RECEIVEDCOL: Receiver 1 vc0 data packet receivedBGP_COL_AR1_VC1_DATA_PACKETS_RECEIVEDCOL: Receiver 1 vc1 data packet receivedBGP_COL_AR2_VC0_DATA_PACKETS_RECEIVEDCOL: Receiver 2 vc0 data packet receivedBGP_COL_AR2_VC1_DATA_PACKETS_RECEIVEDCOL: Receiver 2 vc1 data packet receivedBGP_COL_AS0_VC0_DATA_PACKETS_SENTCOL: Sender 0 vc0 DATA packets sentBGP_COL_AS0_VC1_DATA_PACKETS_SENTCOL: Sender 0 vc1 DATA packets sentBGP_COL_AS1_VC0_DATA_PACKETS_SENTCOL: Sender 1 vc0 DATA packets sentBGP_COL_AS1_VC1_DATA_PACKETS_SENTCOL: Sender 1 vc1 DATA packets sentBGP_COL_AS2_VC0_DATA_PACKETS_SENTCOL: Sender 2 vc0 DATA packets sentBGP_COL_AS2_VC1_DATA_PACKETS_SENTCOL: Sender 2 vc1 DATA packets sentBGP_COL_INJECT_VC0_HEADERCOL: Injection vc0 headerBGP_COL_INJECT_VC1_HEADERCOL: Injection vc1 header addedBGP_COL_RECEPTION_VC0_PACKET_ADDEDCOL: Reception vc0 packet addedBGP_COL_RECEPTION_VC1_PACKET_ADDEDCOL: Reception vc1 packet addedBGP_IC_TIMESTAMPIC: TimestampReservedReservedReservedReservedBGP_MISC_ELAPSED_TIMEMISC: Elapsed running timeBGP_PU2_JPIPE_INSTRUCTIONSP2 CPU: J-pipe instructionsBGP_PU2_JPIPE_ADD_SUBP2 CPU: Add/Sub in J-pipeBGP_PU2_JPIPE_LOGICAL_OPSP2 CPU: Logical operations in J-pipeBGP_PU2_JPIPE_SHROTMKP2 CPU: J-pipe shift/rotate/mask instructionBGP_PU2_IPIPE_INSTRUCTIONSP2 CPU: I-pipe instructionsBGP_PU2_IPIPE_MULT_DIVP2 CPU: Mult/Div in I-pipeBGP_PU2_IPIPE_ADD_SUBP2 CPU: Add/Sub in I-pipeBGP_PU2_IPIPE_LOGICAL_OPSP2 CPU: Logical operations in I-pipeBGP_PU2_IPIPE_SHROTMKP2 CPU: I-pipe shift/rotate/mask instructionBGP_PU2_IPIPE_BRANCHESP2 CPU: BranchesBGP_PU2_IPIPE_TLB_OPSP2 CPU: TLB operationsBGP_PU2_IPIPE_PROCESS_CONTROLP2 CPU: Process controlBGP_PU2_IPIPE_OTHERP2 CPU: Other I-pipe operationsBGP_PU2_DCACHE_LINEFILLINPROGP2 CPU: Cycles for data cache LineFillInProgressBGP_PU2_ICACHE_LINEFILLINPROGP2 CPU: Cycles for inst cache LineFillInProgressBGP_PU2_DCACHE_MISSP2 CPU: Accesses to data cache which missed data cacheBGP_PU2_DCACHE_HITP2 CPU: Accesses to data cache which hit data cacheBGP_PU2_DATA_LOADSP2 CPU: Data loadsBGP_PU2_DATA_STORESP2 CPU: Data storesBGP_PU2_DCACHE_OPSP2 CPU: Data cache operationsBGP_PU2_ICACHE_MISSP2 CPU: Accesses to inst cache which missed inst cacheBGP_PU2_ICACHE_HITP2 CPU: Accesses to inst cache which hit inst cacheBGP_PU2_FPU_ADD_SUB_1P2 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU2_FPU_MULT_1P2 FPU: Mult: fmul fmulsBGP_PU2_FPU_FMA_2P2 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU2_FPU_DIV_1P2 FPU: Div: fdiv, fdivsBGP_PU2_FPU_OTHER_NON_STORAGE_OPSP2 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb3BGP_PU2_FPU_ADD_SUB_2P2 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU2_FPU_MULT_2P2 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU2_FPU_FMA_4P2 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU2_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPSP2 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU2_FPU_QUADWORD_LOADSP2 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU2_FPU_OTHER_LOADSP2 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU2_FPU_QUADWORD_STORESP2 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU2_FPU_OTHER_STORESP2 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU3_JPIPE_INSTRUCTIONSP3 CPU: J-pipe instructionsBGP_PU3_JPIPE_ADD_SUBP3 CPU: Add/Sub in J-pipeBGP_PU3_JPIPE_LOGICAL_OPSP3 CPU: Logical operations in J-pipeBGP_PU3_JPIPE_SHROTMKP3 CPU: J-pipe shift/rotate/mask instructionBGP_PU3_IPIPE_INSTRUCTIONSP3 CPU: I-pipe instructionsBGP_PU3_IPIPE_MULT_DIVP3 CPU: Mult/Div in I-pipeBGP_PU3_IPIPE_ADD_SUBP3 CPU: Add/Sub in I-pipeBGP_PU3_IPIPE_LOGICAL_OPSP3 CPU: Logical operations in I-pipeBGP_PU3_IPIPE_SHROTMKP3 CPU: I-pipe shift/rotate/mask instructionBGP_PU3_IPIPE_BRANCHESP3 CPU: BranchesBGP_PU3_IPIPE_TLB_OPSP3 CPU: TLB operationsBGP_PU3_IPIPE_PROCESS_CONTROLP3 CPU: Process controlBGP_PU3_IPIPE_OTHERP3 CPU: Other I-pipe operationsBGP_PU3_DCACHE_LINEFILLINPROGP3 CPU: Cycles for data cache LineFillInProgressBGP_PU3_ICACHE_LINEFILLINPROGP3 CPU: Cycles for inst cache LineFillInProgressBGP_PU3_DCACHE_MISSP3 CPU: Accesses to data cache which missed data cacheBGP_PU3_DCACHE_HITP3 CPU: Accesses to data cache which hit data cacheBGP_PU3_DATA_LOADSP3 CPU: Data loadsBGP_PU3_DATA_STORESP3 CPU: Data storesBGP_PU3_DCACHE_OPSP3 CPU: Data cache operationsBGP_PU3_ICACHE_MISSP3 CPU: Accesses to inst cache which missed inst cacheBGP_PU3_ICACHE_HITP3 CPU: Accesses to inst cache which hit inst cacheBGP_PU3_FPU_ADD_SUB_1P3 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU3_FPU_MULT_1P3 FPU: Mult: fmul fmulsBGP_PU3_FPU_FMA_2P3 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU3_FPU_DIV_1P3 FPU: Div: fdiv, fdivsBGP_PU3_FPU_OTHER_NON_STORAGE_OPSP3 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb4BGP_PU3_FPU_ADD_SUB_2P3 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU3_FPU_MULT_2P3 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU3_FPU_FMA_4P3 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU3_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPSP3 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU3_FPU_QUADWORD_LOADSP3 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU3_FPU_OTHER_LOADSP3 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU3_FPU_QUADWORD_STORESP3 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU3_FPU_OTHER_STORESP3 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU2_L1_INVALIDATION_REQUESTSP2 L1: Invalidation requestedBGP_PU3_L1_INVALIDATION_REQUESTSP3 L1: Invalidation requestedBGP_COL_AC_CH2_VC0_MATURE_UM1COL: Arbiter_core ch2_vc0_matureBGP_COL_AC_CH1_VC0_MATURE_UM1COL: Arbiter_core ch1_vc0_matureBGP_COL_AC_CH0_VC0_MATURE_UM1COL: Arbiter_core ch0_vc0_matureBGP_COL_AC_INJECT_VC0_MATURE_UM1COL: Arbiter_core inj_vc0_matureBGP_COL_AC_CH2_VC1_MATURE_UM1COL: Arbiter_core ch2_vc1_matureBGP_COL_AC_CH1_VC1_MATURE_UM1COL: Arbiter_core ch1_vc1_matureBGP_COL_AC_CH0_VC1_MATURE_UM1COL: Arbiter_core ch0_vc1_matureBGP_COL_AC_INJECT_VC1_MATURE_UM1COL: Arbiter_core inj_vc1_matureBGP_COL_AR0_VC0_EMPTY_PACKETCOL: Receiver 0 vc0 empty packetBGP_COL_AR0_VC1_EMPTY_PACKETCOL: Receiver 0 vc1 empty packetBGP_COL_AR0_IDLE_PACKETCOL: Receiver 0 IDLE packetBGP_COL_AR0_BAD_PACKET_MARKERCOL: Receiver 0 known-bad-packet markerBGP_COL_AR0_VC0_CUT_THROUGHCOL: Receiver 0 vc0 cut-throughBGP_COL_AR0_VC1_CUT_THROUGHCOL: Receiver 0 vc1 cut-throughBGP_COL_AR0_HEADER_PARITY_ERRORCOL: Receiver 0 header parity errorBGP_COL_AR0_UNEXPECTED_HEADER_ERRORCOL: Receiver 0 unexpected header errorBGP_COL_AR0_RESYNCCOL: Receiver 0 resynch-mode (after error)BGP_COL_AR1_VC0_EMPTY_PACKETCOL: Receiver 1 vc0 empty packetBGP_COL_AR1_VC1_EMPTY_PACKETCOL: Receiver 1 vc1 empty packetBGP_COL_AR1_IDLE_PACKETCOL: Receiver 1 IDLE packetBGP_COL_AR1_BAD_PACKET_MARKERCOL: Receiver 1 known-bad-packet markerBGP_COL_AR1_VC0_CUT_THROUGHCOL: Receiver 1 vc0 cut-throughBGP_COL_AR1_VC1_CUT_THROUGHCOL: Receiver 1 vc1 cut-throughBGP_COL_AR1_HEADER_PARITY_ERRORCOL: Receiver 1 header parity errorBGP_COL_AR1_UNEXPECTED_HEADER_ERRORCOL: Receiver 1 unexpected header errorBGP_COL_AR1_RESYNCCOL: Receiver 1 resynch-mode (after error)BGP_COL_AR2_VC0_EMPTY_PACKETCOL: Receiver 2 vc0 empty packetBGP_COL_AR2_VC1_EMPTY_PACKETCOL: Receiver 2 vc1 empty packetBGP_COL_AR2_IDLE_PACKETCOL: Receiver 2 IDLE packetBGP_COL_AR2_BAD_PACKET_MARKERCOL: Receiver 2 known-bad-packet markerBGP_COL_AR2_VC0_CUT_THROUGHCOL: Receiver 2 vc0 cut-throughBGP_COL_AR2_VC1_CUT_THROUGHCOL: Receiver 2 vc1 cut-throughBGP_COL_AR2_HEADER_PARITY_ERRORCOL: Receiver 2 header parity errorBGP_COL_AR2_UNEXPECTED_HEADER_ERRORCOL: Receiver 2 unexpected header errorBGP_COL_AR2_RESYNCCOL: Receiver 2 resynch-mode (after error)BGP_COL_AS0_VC0_CUT_THROUGHCOL: Sender 0 vc0 cut-throughBGP_COL_AS0_VC1_CUT_THROUGHCOL: Sender 0 vc1 cut-throughBGP_COL_AS0_VC0_PACKETS_SENTCOL: Sender 0 vc0 packet sent (total)BGP_COL_AS0_VC1_PACKETS_SENTCOL: Sender 0 vc1 packet sent (total)BGP_COL_AS0_IDLE_PACKETS_SENTCOL: Sender 0 IDLE packets sentBGP_COL_AS1_VC0_CUT_THROUGHCOL: Sender 1 vc0 cut-throughBGP_COL_AS1_VC1_CUT_THROUGHCOL: Sender 1 vc1 cut-throughBGP_COL_AS1_VC0_PACKETS_SENTCOL: Sender 1 vc0 packet sent (total)BGP_COL_AS1_VC1_PACKETS_SENTCOL: Sender 1 vc1 packet sent (total)BGP_COL_AS1_IDLE_PACKETS_SENTCOL: Sender 1 IDLE packets sentBGP_COL_AS2_VC0_CUT_THROUGHCOL: Sender 2 vc0 cut-throughBGP_COL_AS2_VC1_CUT_THROUGHCOL: Sender 2 vc1 cut-throughBGP_COL_AS2_VC0_PACKETS_SENTCOL: Sender 2 vc0 packet sent (total)BGP_COL_AS2_VC1_PACKETS_SENTCOL: Sender 2 vc1 packet sent (total)BGP_COL_AS2_IDLE_PACKETS_SENTCOL: Sender 2 IDLE packets sentBGP_COL_INJECT_VC0_PAYLOAD_ADDEDCOL: Injection vc0 payload addedBGP_COL_INJECT_VC1_PAYLOAD_ADDEDCOL: Injection vc1 payload addedBGP_COL_INJECT_VC0_PACKET_TAKENCOL: Injection vc0 packet takenBGP_COL_INJECT_VC1_PACKET_TAKENCOL: Injection vc1 packet takenBGP_COL_RECEPTION_VC0_HEADER_TAKENCOL: Reception vc0 header takenBGP_COL_RECEPTION_VC1_HEADER_TAKENCOL: Reception vc1 header takenBGP_COL_RECEPTION_VC0_PAYLOAD_TAKENCOL: Reception vc0 payload takenBGP_COL_RECEPTION_VC1_PAYLOAD_TAKENCOL: Reception vc1 payload takenBGP_COL_RECEPTION_VC0_PACKET_DISCARDEDCOL: Reception vc0 packet discardedBGP_COL_RECEPTION_VC1_PACKET_DISCARDEDCOL: Reception vc1 packet discardedBGP_PU2_L2_VALID_PREFETCH_REQUESTSP2 L2: Pre-fetch request validBGP_PU2_L2_PREFETCH_HITS_IN_FILTERP2 L2: Pre-fetch hits in filterBGP_PU2_L2_PREFETCH_HITS_IN_STREAMP2 L2: Pre-fetch hits in active streamBGP_PU2_L2_CYCLES_PREFETCH_PENDINGP2 L2: Number of cycles for which L2 pre-fetch is pendingBGP_PU2_L2_PAGE_ALREADY_IN_L2P2 L2: Requested PF is already in L2BGP_PU2_L2_PREFETCH_SNOOP_HIT_SAME_COREP2 L2: Pre-fetch snoop hit from same core (write)BGP_PU2_L2_PREFETCH_SNOOP_HIT_OTHER_COREP2 L2: Pre-fetch snoop hit from other coreBGP_PU2_L2_PREFETCH_SNOOP_HIT_PLBP2 L2: Pre-fetch snoop hit PLB (write)BGP_PU2_L2_CYCLES_READ_REQUEST_PENDINGP2 L2: Number of cycles for which read request is pendingBGP_PU2_L2_READ_REQUESTSP2 L2: Read requestsBGP_PU2_L2_DEVBUS_READ_REQUESTSP2 L2: Devbus read requests (SRAM, LOCK, and UPC)BGP_PU2_L2_L3_READ_REQUESTSP2 L2: L3 read requestBGP_PU2_L2_NETBUS_READ_REQUESTSP2 L2: Netbus read requests (tree and torus)BGP_PU2_L2_BLIND_DEV_READ_REQUESTSP2 L2: Blind device read requestBGP_PU2_L2_PREFETCHABLE_REQUESTSP2 L2: Pre-fetchable requestsBGP_PU2_L2_HITP2 L2: L2 hitBGP_PU2_L2_SAME_CORE_SNOOPSP2 L2: Same core snoopsBGP_PU2_L2_OTHER_CORE_SNOOPSP2 L2: Other core snoopsBGP_PU2_L2_OTHER_DP_PU0_SNOOPSP2 L2: Other DP PU0 snoopsBGP_PU2_L2_OTHER_DP_PU1_SNOOPSP2 L2: Other DP PU1 snoopsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReserved BGP_PU2_L2_MEMORY_WRITESP2 L2: Writes to memory BGP_PU2_L2_NETWORK_WRITESP2 L2: Writes to networkBGP_PU2_L2_DEVBUS_WRITESP2 L2: Writes to devbusBGP_PU3_L2_VALID_PREFETCH_REQUESTSP3 L2: Pre-fetch request validBGP_PU3_L2_PREFETCH_HITS_IN_FILTERP3 L2: Pre-fetch hits in filterBGP_PU3_L2_PREFETCH_HITS_IN_STREAMP3 L2: Pre-fetch hits in active streamBGP_PU3_L2_CYCLES_PREFETCH_PENDINGP3 L2: Number of cycles for which L2 pre-fetch is pendingBGP_PU3_L2_PAGE_ALREADY_IN_L2P3 L2: Requested PF is already in L2BGP_PU3_L2_PREFETCH_SNOOP_HIT_SAME_COREP3 L2: Pre-fetch snoop hit from same core (write)BGP_PU3_L2_PREFETCH_SNOOP_HIT_OTHER_COREP3 L2: Pre-fetch snoop hit from other coreBGP_PU3_L2_PREFETCH_SNOOP_HIT_PLBP3 L2: Pre-fetch snoop hit PLB (write)BGP_PU3_L2_CYCLES_READ_REQUEST_PENDINGP3 L2: Number of cycles for which read request is pendingBGP_PU3_L2_READ_REQUESTSP3 L2: Read requestsBGP_PU3_L2_DEVBUS_READ_REQUESTSP3 L2: Devbus read requests (SRAM, LOCK, and UPC)BGP_PU3_L2_L3_READ_REQUESTSP3 L2: L3 read requestBGP_PU3_L2_NETBUS_READ_REQUESTSP3 L2: Netbus read requests (tree and torus)BGP_PU3_L2_BLIND_DEV_READ_REQUESTSP3 L2: Blind device read requestBGP_PU3_L2_PREFETCHABLE_REQUESTSP3 L2: Pre-fetchable requestsBGP_PU3_L2_HITP3 L2: L2 hitBGP_PU3_L2_SAME_CORE_SNOOPSP3 L2: Same core snoopsBGP_PU3_L2_OTHER_CORE_SNOOPSP3 L2: Other core snoopsBGP_PU3_L2_OTHER_DP_PU0_SNOOPSP3 L2: Other DP PU0 snoopsBGP_PU3_L2_OTHER_DP_PU1_SNOOPSP3 L2: Other DP PU1 snoopsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReserved BGP_PU3_L2_MEMORY_WRITESP3 L2: Writes to memory BGP_PU3_L2_NETWORK_WRITESP3 L2: Writes to networkBGP_PU3_L2_DEVBUS_WRITESP3 L2: Writes to devbusBGP_L3_M0_R2_SINGLE_LINE_DELIVERED_L2L3 M0 Rd 2: Single line delivered to L2BGP_L3_M0_R2_BURST_DELIVERED_L2L3 M0 Rd 2: Burst delivered to L2BGP_L3_M0_R2_READ_RETURN_COLLISIONL3 M0 Rd 2: Read return collisionBGP_L3_M0_R2_DIR0_HIT_OR_INFLIGHTL3 M0 Rd 2: dir0 hit or in flightBGP_L3_M0_R2_DIR0_MISS_OR_LOCKDOWNL3 M0 Rd 2: dir0 miss or lock-downBGP_L3_M0_R2_DIR1_HIT_OR_INFLIGHTL3 M0 Rd 2: dir1 hit or in flightBGP_L3_M0_R2_DIR1_MISS_OR_LOCKDOWNL3 M0 Rd 2: dir1 miss or lock-downBGP_L3_M0_W0_DEPOSIT_REQUESTSL3 M0 WRB 0: Total accepted deposit requests from write queues to write bufferBGP_L3_M0_W0_CYCLES_REQUESTS_NOT_TAKENL3 M0 WRB 0: Number of cycles with requests from queues that are not takenBGP_L3_M0_W1_DEPOSIT_REQUESTSL3 M0 WRB 1: Total accepted deposit requests from write queues to write bufferBGP_L3_M0_W1_CYCLES_REQUESTS_NOT_TAKENL3 M0 WRB 1: Number of cycles with requests from queues that are not takenBGP_L3_M0_MH_ALLOCATION_REQUESTSL3 M0 MH: Number of allocation requests to write bufferBGP_L3_M0_MH_CYCLES_ALLOCATION_REQUESTS_NOT_TAKENL3 M0 MH: Number of allocation request cycles to write buffer without being takenBGP_L3_M0_PF_PREFETCH_INTO_EDRAML3 M0 PF: Number of line pre-fetches brought into eDRAMReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedBGP_L3_M1_R2_SINGLE_LINE_DELIVERED_L2L3 M1 Rd 2: Single line delivered to L2BGP_L3_M1_R2_BURST_DELIVERED_L2L3 M1 Rd 2: Burst delivered to L2BGP_L3_M1_R2_READ_RETURN_COLLISIONL3 M1 Rd 2: Read return collisionBGP_L3_M1_R2_DIR0_HIT_OR_INFLIGHTL3 M1 Rd 2: dir0 hit or in flightBGP_L3_M1_R2_DIR0_MISS_OR_LOCKDOWNL3 M1 Rd 2: dir0 miss or lock-downBGP_L3_M1_R2_DIR1_HIT_OR_INFLIGHTL3 M1 Rd 2: dir1 hit or in flightBGP_L3_M1_R2_DIR1_MISS_OR_LOCKDOWNL3 M1 Rd 2: dir1 miss or lock-downBGP_L3_M1_W0_DEPOSIT_REQUESTSL3 M1 WRB 0: Total accepted deposit requests from write queues to write bufferBGP_L3_M1_W0_CYCLES_REQUESTS_NOT_TAKENL3 M1 WRB 0: Number of cycles with requests from queues that are not takenBGP_L3_M1_W1_DEPOSIT_REQUESTSL3 M1 WRB 1: Total accepted deposit requests from write queues to write bufferBGP_L3_M1_W1_CYCLES_REQUESTS_NOT_TAKENL3 M1 WRB 1: Number of cycles with requests from queues that are not takenBGP_L3_M1_MH_ALLOCATION_REQUESTSL3 M1 MH: Number of allocation requests to write bufferBGP_L3_M1_MH_CYCLES_ALLOCATION_REQUESTS_NOT_TAKENL3 M1 MH: Number of allocation request cycles to write buffer without being takenBGP_L3_M1_PF_PREFETCH_INTO_EDRAML3 M1 PF: Number of line pre-fetches brought into eDRAMReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedBGP_PU2_SNOOP_PORT0_REMOTE_SOURCE_REQUESTSP2 SNP: Port 0 received a snoop request from a remote sourceBGP_PU2_SNOOP_PORT1_REMOTE_SOURCE_REQUESTSP2 SNP: Port 1 received a snoop request from a remote sourceBGP_PU2_SNOOP_PORT2_REMOTE_SOURCE_REQUESTSP2 SNP: Port 2 received a snoop request from a remote sourceBGP_PU2_SNOOP_PORT3_REMOTE_SOURCE_REQUESTSP2 SNP: Port 3 received a snoop request from a remote sourceBGP_PU2_SNOOP_PORT0_REJECTED_REQUESTSP2 SNP: Port 0 snoop filter rejected a snoop requestBGP_PU2_SNOOP_PORT1_REJECTED_REQUESTSP2 SNP: Port 1 snoop filter rejected a snoop requestBGP_PU2_SNOOP_PORT2_REJECTED_REQUESTSP2 SNP: Port 2 snoop filter rejected a snoop requestBGP_PU2_SNOOP_PORT3_REJECTED_REQUESTSP2 SNP: Port 3 snoop filter rejected a snoop requestBGP_PU2_SNOOP_L1_CACHE_WRAPP2 SNP: Snoop filter detected an L1 cache wrapBGP_PU3_SNOOP_PORT0_REMOTE_SOURCE_REQUESTSP3 SNP: Port 0 received a snoop request from a remote sourceBGP_PU3_SNOOP_PORT1_REMOTE_SOURCE_REQUESTSP3 SNP: Port 1 received a snoop request from a remote sourceBGP_PU3_SNOOP_PORT2_REMOTE_SOURCE_REQUESTSP3 SNP: Port 2 received a snoop request from a remote sourceBGP_PU3_SNOOP_PORT3_REMOTE_SOURCE_REQUESTSP3 SNP: Port 3 received a snoop request from a remote sourceBGP_PU3_SNOOP_PORT0_REJECTED_REQUESTSP3 SNP: Port 0 snoop filter rejected a snoop requestBGP_PU3_SNOOP_PORT1_REJECTED_REQUESTSP3 SNP: Port 1 snoop filter rejected a snoop requestBGP_PU3_SNOOP_PORT2_REJECTED_REQUESTSP3 SNP: Port 2 snoop filter rejected a snoop requestBGP_PU3_SNOOP_PORT3_REJECTED_REQUESTSP3 SNP: Port 3 snoop filter rejected a snoop requestBGP_PU3_SNOOP_L1_CACHE_WRAPP3 SNP: Snoop filter detected an L1 cache wrapReservedReservedBGP_MISC_ELAPSED_TIME_UM1MISC: Elapsed running timeBGP_PU0_JPIPE_INSTRUCTIONS_UM2P0 CPU: J-pipe instructionsBGP_PU0_JPIPE_ADD_SUB_UM2P0 CPU: Add/Sub in J-pipeBGP_PU0_JPIPE_LOGICAL_OPS_UM2P0 CPU: Logical operations in J-pipeBGP_PU0_JPIPE_SHROTMK_UM2P0 CPU: J-pipe shift/rotate/mask instructionBGP_PU0_IPIPE_INSTRUCTIONS_UM2P0 CPU: I-pipe instructionsBGP_PU0_IPIPE_MULT_DIV_UM2P0 CPU: Mult/Div in I-pipeBGP_PU0_IPIPE_ADD_SUB_UM2P0 CPU: Add/Sub in I-pipeBGP_PU0_IPIPE_LOGICAL_OPS_UM2P0 CPU: Logical operations in I-pipeBGP_PU0_IPIPE_SHROTMK_UM2P0 CPU: I-pipe shift/rotate/mask instructionBGP_PU0_IPIPE_BRANCHES_UM2P0 CPU: BranchesBGP_PU0_IPIPE_TLB_OPS_UM2P0 CPU: TLB operationsBGP_PU0_IPIPE_PROCESS_CONTROL_UM2P0 CPU: Process controlBGP_PU0_IPIPE_OTHER_UM2P0 CPU: Other I-pipe operationsBGP_PU0_DCACHE_LINEFILLINPROG_UM2P0 CPU: Cycles for data cache LineFillInProgressBGP_PU0_ICACHE_LINEFILLINPROG_UM2P0 CPU: Cycles for inst cache LineFillInProgressBGP_PU0_DCACHE_MISS_UM2P0 CPU: Accesses to data cache which missed data cacheBGP_PU0_DCACHE_HIT_UM2P0 CPU: Accesses to data cache which hit data cacheBGP_PU0_DATA_LOADS_UM2P0 CPU: Data loadsBGP_PU0_DATA_STORES_UM2P0 CPU: Data storesBGP_PU0_DCACHE_OPS_UM2P0 CPU: Data cache operationsBGP_PU0_ICACHE_MISS_UM2P0 CPU: Accesses to inst cache which missed inst cacheBGP_PU0_ICACHE_HIT_UM2P0 CPU: Accesses to inst cache which hit inst cacheBGP_PU0_FPU_ADD_SUB_1_UM2P0 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU0_FPU_MULT_1_UM2P0 FPU: Mult: fmul fmulsBGP_PU0_FPU_FMA_2_UM2P0 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU0_FPU_DIV_1_UM2P0 FPU: Div: fdiv, fdivsBGP_PU0_FPU_OTHER_NON_STORAGE_OPS_UM2P0 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb1BGP_PU0_FPU_ADD_SUB_2_UM2P0 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU0_FPU_MULT_2_UM2P0 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU0_FPU_FMA_4_UM2P0 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU0_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS_UM2P0 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU0_FPU_QUADWORD_LOADS_UM2P0 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU0_FPU_OTHER_LOADS_UM2P0 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU0_FPU_QUADWORD_STORES_UM2P0 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU0_FPU_OTHER_STORES_UM2P0 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU1_JPIPE_INSTRUCTIONS_UM2P1 CPU: J-pipe instructionsBGP_PU1_JPIPE_ADD_SUB_UM2P1 CPU: Add/Sub in J-pipeBGP_PU1_JPIPE_LOGICAL_OPS_UM2P1 CPU: Logical operations in J-pipeBGP_PU1_JPIPE_SHROTMK_UM2P1 CPU: J-pipe shift/rotate/mask instructionBGP_PU1_IPIPE_INSTRUCTIONS_UM2P1 CPU: I-pipe instructionsBGP_PU1_IPIPE_MULT_DIV_UM2P1 CPU: Mult/Div in I-pipeBGP_PU1_IPIPE_ADD_SUB_UM2P1 CPU: Add/Sub in I-pipeBGP_PU1_IPIPE_LOGICAL_OPS_UM2P1 CPU: Logical operations in I-pipeBGP_PU1_IPIPE_SHROTMK_UM2P1 CPU: I-pipe shift/rotate/mask instructionBGP_PU1_IPIPE_BRANCHES_UM2P1 CPU: BranchesBGP_PU1_IPIPE_TLB_OPS_UM2P1 CPU: TLB operationsBGP_PU1_IPIPE_PROCESS_CONTROL_UM2P1 CPU: Process controlBGP_PU1_IPIPE_OTHER_UM2P1 CPU: Other I-pipe operationsBGP_PU1_DCACHE_LINEFILLINPROG_UM2P1 CPU: Cycles for data cache LineFillInProgressBGP_PU1_ICACHE_LINEFILLINPROG_UM2P1 CPU: Cycles for inst cache LineFillInProgressBGP_PU1_DCACHE_MISS_UM2P1 CPU: Accesses to data cache which missed data cacheBGP_PU1_DCACHE_HIT_UM2P1 CPU: Accesses to data cache which hit data cacheBGP_PU1_DATA_LOADS_UM2P1 CPU: Data loadsBGP_PU1_DATA_STORES_UM2P1 CPU: Data storesBGP_PU1_DCACHE_OPS_UM2P1 CPU: Data cache operationsBGP_PU1_ICACHE_MISS_UM2P1 CPU: Accesses to inst cache which missed inst cacheBGP_PU1_ICACHE_HIT_UM2P1 CPU: Accesses to inst cache which hit inst cacheBGP_PU1_FPU_ADD_SUB_1_UM2P1 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU1_FPU_MULT_1_UM2P1 FPU: Mult: fmul fmulsBGP_PU1_FPU_FMA_2_UM2P1 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU1_FPU_DIV_1_UM2P1 FPU: Div: fdiv, fdivsBGP_PU1_FPU_OTHER_NON_STORAGE_OPS_UM2P1 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb2BGP_PU1_FPU_ADD_SUB_2_UM2P1 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU1_FPU_MULT_2_UM2P1 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU1_FPU_FMA_4_UM2P1 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU1_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS_UM2P1 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU1_FPU_QUADWORD_LOADS_UM2P1 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU1_FPU_OTHER_LOADS_UM2P1 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU1_FPU_QUADWORD_STORES_UM2P1 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU1_FPU_OTHER_STORES_UM2P1 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU0_L1_INVALIDATION_UM2P0 L1: Invalidation requestedBGP_PU1_L1_INVALIDATION_UM2P1 L1: Invalidation requestedBGP_PU0_SNOOP_PORT0_CACHE_REJECTED_REQUESTP0 SNP: Port 0 snoop cache rejected a requestBGP_PU0_SNOOP_PORT1_CACHE_REJECTED_REQUESTP0 SNP: Port 1 snoop cache rejected a requestBGP_PU0_SNOOP_PORT2_CACHE_REJECTED_REQUESTP0 SNP: Port 2 snoop cache rejected a requestBGP_PU0_SNOOP_PORT3_CACHE_REJECTED_REQUESTP0 SNP: Port 3 snoop cache rejected a requestBGP_PU0_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_ACTIVE_SETP0 SNP: Port 0 request hit a stream register in the active setBGP_PU0_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_ACTIVE_SETP0 SNP: Port 1 request hit a stream register in the active setBGP_PU0_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_ACTIVE_SETP0 SNP: Port 2 request hit a stream register in the active setBGP_PU0_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_ACTIVE_SETP0 SNP: Port 3 request hit a stream register in the active setBGP_PU0_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_HISTORY_SETP0 SNP: Port 0 request hit a stream register in the history setBGP_PU0_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_HISTORY_SETP0 SNP: Port 1 request hit a stream register in the history setBGP_PU0_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_HISTORY_SETP0 SNP: Port 2 request hit a stream register in the history setBGP_PU0_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_HISTORY_SETP0 SNP: Port 3 request hit a stream register in the history setBGP_PU0_SNOOP_PORT0_STREAM_REGISTER_REJECTED_REQUESTP0 SNP: Port 0 stream register rejected a requestBGP_PU0_SNOOP_PORT1_STREAM_REGISTER_REJECTED_REQUESTP0 SNP: Port 1 stream register rejected a requestBGP_PU0_SNOOP_PORT2_STREAM_REGISTER_REJECTED_REQUESTP0 SNP: Port 2 stream register rejected a requestBGP_PU0_SNOOP_PORT3_STREAM_REGISTER_REJECTED_REQUESTP0 SNP: Port 3 stream register rejected a requestBGP_PU0_SNOOP_PORT0_RANGE_FILTER_REJECTED_REQUESTP0 SNP: Port 0 range filter rejected a requestBGP_PU0_SNOOP_PORT1_RANGE_FILTER_REJECTED_REQUESTP0 SNP: Port 1 range filter rejected a requestBGP_PU0_SNOOP_PORT2_RANGE_FILTER_REJECTED_REQUESTP0 SNP: Port 2 range filter rejected a requestBGP_PU0_SNOOP_PORT3_RANGE_FILTER_REJECTED_REQUESTP0 SNP: Port 3 range filter rejected a requestBGP_PU0_SNOOP_PORT0_UPDATED_CACHE_LINEP0 SNP: Port 0 snoop cache updated cache lineBGP_PU0_SNOOP_PORT1_UPDATED_CACHE_LINEP0 SNP: Port 1 snoop cache updated cache lineBGP_PU0_SNOOP_PORT2_UPDATED_CACHE_LINEP0 SNP: Port 2 snoop cache updated cache lineBGP_PU0_SNOOP_PORT3_UPDATED_CACHE_LINEP0 SNP: Port 3 snoop cache updated cache lineBGP_PU0_SNOOP_PORT0_FILTERED_BY_CACHE_AND_REGISTERSP0 SNP: Port 0 snoop filtered by both snoop cache and filter registersBGP_PU0_SNOOP_PORT1_FILTERED_BY_CACHE_AND_REGISTERSP0 SNP: Port 1 snoop filtered by both snoop cache and filter registersBGP_PU0_SNOOP_PORT2_FILTERED_BY_CACHE_AND_REGISTERSP0 SNP: Port 2 snoop filtered by both snoop cache and filter registersBGP_PU0_SNOOP_PORT3_FILTERED_BY_CACHE_AND_REGISTERSP0 SNP: Port 3 snoop filtered by both snoop cache and filter registersBGP_PU1_SNOOP_PORT0_CACHE_REJECTED_REQUESTP1 SNP: Port 0 snoop cache rejected a requestBGP_PU1_SNOOP_PORT1_CACHE_REJECTED_REQUESTP1 SNP: Port 1 snoop cache rejected a requestBGP_PU1_SNOOP_PORT2_CACHE_REJECTED_REQUESTP1 SNP: Port 2 snoop cache rejected a requestBGP_PU1_SNOOP_PORT3_CACHE_REJECTED_REQUESTP1 SNP: Port 3 snoop cache rejected a requestBGP_PU1_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_ACTIVE_SETP1 SNP: Port 0 request hit a stream register in the active setBGP_PU1_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_ACTIVE_SETP1 SNP: Port 1 request hit a stream register in the active setBGP_PU1_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_ACTIVE_SETP1 SNP: Port 2 request hit a stream register in the active setBGP_PU1_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_ACTIVE_SETP1 SNP: Port 3 request hit a stream register in the active setBGP_PU1_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_HISTORY_SETP1 SNP: Port 0 request hit a stream register in the history setBGP_PU1_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_HISTORY_SETP1 SNP: Port 1 request hit a stream register in the history setBGP_PU1_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_HISTORY_SETP1 SNP: Port 2 request hit a stream register in the history setBGP_PU1_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_HISTORY_SETP1 SNP: Port 3 request hit a stream register in the history setBGP_PU1_SNOOP_PORT0_STREAM_REGISTER_REJECTED_REQUESTP1 SNP: Port 0 stream register rejected a requestBGP_PU1_SNOOP_PORT1_STREAM_REGISTER_REJECTED_REQUESTP1 SNP: Port 1 stream register rejected a requestBGP_PU1_SNOOP_PORT2_STREAM_REGISTER_REJECTED_REQUESTP1 SNP: Port 2 stream register rejected a requestBGP_PU1_SNOOP_PORT3_STREAM_REGISTER_REJECTED_REQUESTP1 SNP: Port 3 stream register rejected a requestBGP_PU1_SNOOP_PORT0_RANGE_FILTER_REJECTED_REQUESTP1 SNP: Port 0 range filter rejected a requestBGP_PU1_SNOOP_PORT1_RANGE_FILTER_REJECTED_REQUESTP1 SNP: Port 1 range filter rejected a requestBGP_PU1_SNOOP_PORT2_RANGE_FILTER_REJECTED_REQUESTP1 SNP: Port 2 range filter rejected a requestBGP_PU1_SNOOP_PORT3_RANGE_FILTER_REJECTED_REQUESTP1 SNP: Port 3 range filter rejected a requestBGP_PU1_SNOOP_PORT0_UPDATED_CACHE_LINEP1 SNP: Port 0 snoop cache updated cache lineBGP_PU1_SNOOP_PORT1_UPDATED_CACHE_LINEP1 SNP: Port 1 snoop cache updated cache lineBGP_PU1_SNOOP_PORT2_UPDATED_CACHE_LINEP1 SNP: Port 2 snoop cache updated cache lineBGP_PU1_SNOOP_PORT3_UPDATED_CACHE_LINEP1 SNP: Port 3 snoop cache updated cache lineBGP_PU1_SNOOP_PORT0_FILTERED_BY_CACHE_AND_REGISTERSP1 SNP: Port 0 snoop filtered by both snoop cache and filter registersBGP_PU1_SNOOP_PORT1_FILTERED_BY_CACHE_AND_REGISTERSP1 SNP: Port 1 snoop filtered by both snoop cache and filter registersBGP_PU1_SNOOP_PORT2_FILTERED_BY_CACHE_AND_REGISTERSP1 SNP: Port 2 snoop filtered by both snoop cache and filter registersBGP_PU1_SNOOP_PORT3_FILTERED_BY_CACHE_AND_REGISTERSP1 SNP: Port 3 snoop filtered by both snoop cache and filter registersBGP_TORUS_XP_TOKEN_ACK_PACKETSTORUS: Number of protocol token/ack packets in xpBGP_TORUS_XP_ACKSTORUS: Number of protocol ack packets in xpBGP_TORUS_XP_VCD0_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 0BGP_TORUS_XP_VCD1_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 1BGP_TORUS_XP_VCBN_32BCHUNKSTORUS: Number of 32B chunks sent on bubble vc 2BGP_TORUS_XP_VCBP_32BCHUNKSTORUS: Number of 32B chunks sent on priority vc 3BGP_TORUS_XP_NO_TOKENSTORUS: xp link avail, no vcd0 vcd1 tokensBGP_TORUS_XP_NO_VCD0_TOKENSTORUS: xp link avail; no vcd0 vcd; vcbn tokensBGP_TORUS_XP_NO_VCBN_TOKENSTORUS: xp link avail; no vcbn tokensBGP_TORUS_XP_NO_VCBP_TOKENSTORUS: xp link avail; no vcbp tokensBGP_TORUS_XM_TOKEN_ACK_PACKETSTORUS: Number of protocol token/ack packets in xmBGP_TORUS_XM_ACKSTORUS: Number of protocol ack packets in xmBGP_TORUS_XM_VCD0_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 0BGP_TORUS_XM_VCD1_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 1BGP_TORUS_XM_VCBN_32BCHUNKSTORUS: Number of 32B chunks sent on bubble vc 2BGP_TORUS_XM_VCBP_32BCHUNKSTORUS: Number of 32B chunks sent on priority vc 3BGP_TORUS_XM_NO_TOKENSTORUS: xm link avail; no vcd0 vcd1 tokensBGP_TORUS_XM_NO_VCD0_TOKENSTORUS: xm link avail; no vcd0 vcd; vcbn tokensBGP_TORUS_XM_NO_VCBN_TOKENSTORUS: xm link avail; no vcbn tokensBGP_TORUS_XM_NO_VCBP_TOKENSTORUS: xm link avail; no vcbp tokensBGP_TORUS_YP_TOKEN_ACK_PACKETSTORUS: Number of protocol token/ack packets in ypBGP_TORUS_YP_ACKSTORUS: Number of protocol ack packets in ypBGP_TORUS_YP_VCD0_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 0BGP_TORUS_YP_VCD1_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 1BGP_TORUS_YP_VCBN_32BCHUNKSTORUS: Number of 32B chunks sent on bubble vc 2BGP_TORUS_YP_VCBP_32BCHUNKSTORUS: Number of 32B chunks sent on priority vc 3BGP_TORUS_YP_NO_TOKENSTORUS: yp link avail; no vcd0 vcd1tokensBGP_TORUS_YP_NO_VCD0_TOKENSTORUS: yp link avail; no vcd0 vcd; vcbn tokensBGP_TORUS_YP_NO_VCBN_TOKENSTORUS: yp link avail; no vcbn tokensBGP_TORUS_YP_NO_VCBP_TOKENSTORUS: yp link avail; no vcbp tokensBGP_TORUS_YM_TOKEN_ACK_PACKETSTORUS: Number of protocol token/ack packets in ymBGP_TORUS_YM_ACKSTORUS: Number of protocol ack packets in ymBGP_TORUS_YM_VCD0_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 0BGP_TORUS_YM_VCD1_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 1BGP_TORUS_YM_VCBN_32BCHUNKSTORUS: Number of 32B chunks sent on bubble vc 2BGP_TORUS_YM_VCBP_32BCHUNKSTORUS: Number of 32B chunks sent on priority vc 3BGP_TORUS_YM_NO_TOKENSTORUS: ym link avail; no vcd0 vcd1 tokensBGP_TORUS_YM_NO_VCD0_TOKENSTORUS: ym link avail; no vcd0 vcd; vcbn tokensBGP_TORUS_YM_NO_VCBN_TOKENSTORUS: ym link avail; no vcbn tokensBGP_TORUS_YM_NO_VCBP_TOKENSTORUS: ym link avail; no vcbp tokensBGP_TORUS_ZP_TOKEN_ACK_PACKETSTORUS: Number of protocol token/ack packets in zpBGP_TORUS_ZP_ACKSTORUS: Number of protocol ack packets in zpBGP_TORUS_ZP_VCD0_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 0BGP_TORUS_ZP_VCD1_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 1BGP_TORUS_ZP_VCBN_32BCHUNKSTORUS: Number of 32B chunks sent on bubble vc 2BGP_TORUS_ZP_VCBP_32BCHUNKSTORUS: Number of 32B chunks sent on priority vc 3BGP_TORUS_ZP_NO_TOKENSTORUS: zp link avail; no vcd0 vcd1 tokensBGP_TORUS_ZP_NO_VCD0_TOKENSTORUS: zp link avail; no vcd0 vcd; vcbn tokensBGP_TORUS_ZP_NO_VCBN_TOKENSTORUS: zp link avail; no vcbn tokensBGP_TORUS_ZP_NO_VCBP_TOKENSTORUS: zp link avail; no vcbp tokensBGP_TORUS_ZM_TOKEN_ACK_PACKETSTORUS: Number of protocol token/ack packets in zmBGP_TORUS_ZM_ACKSTORUS: Number of protocol ack packets in zmBGP_TORUS_ZM_VCD0_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 0BGP_TORUS_ZM_VCD1_32BCHUNKSTORUS: Number of 32B chunks sent on dynamic vc 1BGP_TORUS_ZM_VCBN_32BCHUNKSTORUS: Number of 32B chunks sent on bubble vc 2BGP_TORUS_ZM_VCBP_32BCHUNKSTORUS: Number of 32B chunks sent on priority vc 3BGP_TORUS_ZM_NO_TOKENSTORUS: zm link avail; no vcd0 vcd1 tokensBGP_TORUS_ZM_NO_VCD0_TOKENSTORUS: zm link avail; no vcd0 vcd; vcbn tokensReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedBGP_COL_AR2_ABORT_UM2COL: Arbiter receiver 2 abortBGP_COL_AR1_ABORT_UM2COL: Arbiter receiver 1 abortBGP_COL_AR0_ABORT_UM2COL: Arbiter receiver 0 abortBGP_COL_A_LOCAL_CLIENT_ABORTCOL: Arbiter local client abortBGP_COL_AR0_VC0_FULLCOL: Receiver 0 vc0 fullBGP_COL_AR0_VC1_FULLCOL: Receiver 0 vc1 fullBGP_COL_AR1_VC0_FULLCOL: Receiver 1 vc0 fullBGP_COL_AR1_VC1_FULLCOL: Receiver 1 vc1 fullBGP_COL_AR2_VC0_FULLCOL: Receiver 2 vc0 fullBGP_COL_AR2_VC1_FULLCOL: Receiver 2 vc1 fullBGP_COL_AS0_VC0_EMPTYCOL: Sender 0 vc0 emptyBGP_COL_AS0_VC1_EMPTYCOL: Sender 0 vc1 emptyBGP_COL_AS0_RESENDSCOL: Sender 0 resend attemptsBGP_COL_AS1_VC0_EMPTYCOL: Sender 1 vc0 emptyBGP_COL_AS1_VC1_EMPTYCOL: Sender 1 vc1 emptyBGP_COL_AS1_RESENDSCOL: Sender 1 resend attemptsBGP_COL_AS2_VC0_EMPTYCOL: Sender 2 vc0 emptyBGP_COL_AS2_VC1_EMPTYCOL: Sender 2 vc1 emptyBGP_COL_AS2_RESENDSCOL: Sender 2 resend attemptsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedBGP_MISC_ELAPSED_TIME_UM2MISC: Elapsed running timeBGP_PU2_JPIPE_INSTRUCTIONS_UM3P2 CPU: J-pipe instructionsBGP_PU2_JPIPE_ADD_SUB_UM3P2 CPU: Add/Sub in J-pipeBGP_PU2_JPIPE_LOGICAL_OPS_UM3P2 CPU: Logical operations in J-pipeBGP_PU2_JPIPE_SHROTMK_UM3P2 CPU: J-pipe shift/rotate/mask instructionBGP_PU2_IPIPE_INSTRUCTIONS_UM3P2 CPU: I-pipe instructionsBGP_PU2_IPIPE_MULT_DIV_UM3P2 CPU: Mult/Div in I-pipeBGP_PU2_IPIPE_ADD_SUB_UM3P2 CPU: Add/Sub in I-pipeBGP_PU2_IPIPE_LOGICAL_OPS_UM3P2 CPU: Logical operations in I-pipeBGP_PU2_IPIPE_SHROTMK_UM3P2 CPU: I-pipe shift/rotate/mask instructionBGP_PU2_IPIPE_BRANCHES_UM3P2 CPU: BranchesBGP_PU2_IPIPE_TLB_OPS_UM3P2 CPU: TLB operationsBGP_PU2_IPIPE_PROCESS_CONTROL_UM3P2 CPU: Process controlBGP_PU2_IPIPE_OTHER_UM3P2 CPU: Other I-pipe operationsBGP_PU2_DCACHE_LINEFILLINPROG_UM3P2 CPU: Cycles for data cache LineFillInProgressBGP_PU2_ICACHE_LINEFILLINPROG_UM3P2 CPU: Cycles for inst cache LineFillInProgressBGP_PU2_DCACHE_MISS_UM3P2 CPU: Accesses to data cache which missed data cacheBGP_PU2_DCACHE_HIT_UM3P2 CPU: Accesses to data cache which hit data cacheBGP_PU2_DATA_LOADS_UM3P2 CPU: Data loadsBGP_PU2_DATA_STORES_UM3P2 CPU: Data storesBGP_PU2_DCACHE_OPS_UM3P2 CPU: Data cache operationsBGP_PU2_ICACHE_MISS_UM3P2 CPU: Accesses to inst cache which missed inst cacheBGP_PU2_ICACHE_HIT_UM3P2 CPU: Accesses to inst cache which hit inst cacheBGP_PU2_FPU_ADD_SUB_1_UM3P2 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU2_FPU_MULT_1_UM3P2 FPU: Mult: fmul fmulsBGP_PU2_FPU_FMA_2_UM3P2 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU2_FPU_DIV_1_UM3P2 FPU: Div: fdiv, fdivsBGP_PU2_FPU_OTHER_NON_STORAGE_OPS_UM3P2 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb3BGP_PU2_FPU_ADD_SUB_2_UM3P2 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU2_FPU_MULT_2_UM3P2 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU2_FPU_FMA_4_UM3P2 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU2_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS_UM3P2 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU2_FPU_QUADWORD_LOADS_UM3P2 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU2_FPU_OTHER_LOADS_UM3P2 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU2_FPU_QUADWORD_STORES_UM3P2 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU2_FPU_OTHER_STORES_UM3P2 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU3_JPIPE_INSTRUCTIONS_UM3P3 CPU: J-pipe instructionsBGP_PU3_JPIPE_ADD_SUB_UM3P3 CPU: Add/Sub in J-pipeBGP_PU3_JPIPE_LOGICAL_OPS_UM3P3 CPU: Logical operations in J-pipeBGP_PU3_JPIPE_SHROTMK_UM3P3 CPU: J-pipe shift/rotate/mask instructionBGP_PU3_IPIPE_INSTRUCTIONS_UM3P3 CPU: I-pipe instructionsBGP_PU3_IPIPE_MULT_DIV_UM3P3 CPU: Mult/Div in I-pipeBGP_PU3_IPIPE_ADD_SUB_UM3P3 CPU: Add/Sub in I-pipeBGP_PU3_IPIPE_LOGICAL_OPS_UM3P3 CPU: Logical operations in I-pipeBGP_PU3_IPIPE_SHROTMK_UM3P3 CPU: I-pipe shift/rotate/mask instructionBGP_PU3_IPIPE_BRANCHES_UM3P3 CPU: BranchesBGP_PU3_IPIPE_TLB_OPS_UM3P3 CPU: TLB operationsBGP_PU3_IPIPE_PROCESS_CONTROL_UM3P3 CPU: Process controlBGP_PU3_IPIPE_OTHER_UM3P3 CPU: Other I-pipe operationsBGP_PU3_DCACHE_LINEFILLINPROG_UM3P3 CPU: Cycles for data cache LineFillInProgressBGP_PU3_ICACHE_LINEFILLINPROG_UM3P3 CPU: Cycles for inst cache LineFillInProgressBGP_PU3_DCACHE_MISS_UM3P3 CPU: Accesses to data cache which missed data cacheBGP_PU3_DCACHE_HIT_UM3P3 CPU: Accesses to data cache which hit data cacheBGP_PU3_DATA_LOADS_UM3P3 CPU: Data loadsBGP_PU3_DATA_STORES_UM3P3 CPU: Data storesBGP_PU3_DCACHE_OPS_UM3P3 CPU: Data cache operationsBGP_PU3_ICACHE_MISS_UM3P3 CPU: Accesses to inst cache which missed inst cacheBGP_PU3_ICACHE_HIT_UM3P3 CPU: Accesses to inst cache which hit inst cacheBGP_PU3_FPU_ADD_SUB_1_UM3P3 FPU: Add/Sub: fadd, fadds, fsub, fsubsBGP_PU3_FPU_MULT_1_UM3P3 FPU: Mult: fmul fmulsBGP_PU3_FPU_FMA_2_UM3P3 FPU: FMA: fmadd, fmadds, fmsub, fmsubs, fnmadd fnmadds, fnmsub, fnmsubs; 1 result generated per instruction, 2 flopsBGP_PU3_FPU_DIV_1_UM3P3 FPU: Div: fdiv, fdivsBGP_PU3_FPU_OTHER_NON_STORAGE_OPS_UM3P3 FPU: other non-storage instructions: fabs, fnabs, frsp, fctiw, fctiw, fctiwz, fres, frsqrte, fsel, fmr fneg, fcmpu, fcmpo, mffs, mcrfs, mtfsfi, mtfsf, mtfsb0, mtfsb4BGP_PU3_FPU_ADD_SUB_2_UM3P3 FPU: Add/Sub Dual Pipe: fpadd fpsubBGP_PU3_FPU_MULT_2_UM3P3 FPU: Mult Dual Pipe: fpmul, fxmul, fxpmul, fxsmulBGP_PU3_FPU_FMA_4_UM3P3 FPU: FMA Dual Pipe: fpmadd, fpnmadd, fpmsub, fpnmsub fxmadd, fxnmadd, fxmsub, fxnmsub fxcpmadd, fxcsmadd, fxcpnmadd fxcsnmadd, fxcpmsub, fxcsmsub fxcpnmsub, fxcsnmsub, fxcpnpma fxcsnpma, fxcpnsma, fxcsnsma fxcxnpma, fxcxnsma, fxcxma, fxcxnms; 2 results generated per instruction, 4 flopsBGP_PU3_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS_UM3P3 FPU: Dual Pipe other non-storage instructions: fpmr, fpneg, fsmr, fsneg, fxmr, fsmfp, fsmtp, fpabs, fpnabs, fsabs, fsnabs, fprsp, fpctiw, fpctiwz, fpre, fprsqrte, fpsel, fscmpBGP_PU3_FPU_QUADWORD_LOADS_UM3P3 FPU: Quad-word Loads: lfpdx, lfpdux, lfxdx, lfxduxBGP_PU3_FPU_OTHER_LOADS_UM3P3 FPU: Other Loads: lfs, lfsx, lfsu, lfsux, lfpsx, fpsux, lfsdx, lfsdux, lfssx, lfssux, lfd, lfdx, lfdu, lfdux, lfxsx, lfxsuxBGP_PU3_FPU_QUADWORD_STORES_UM3P3 FPU: Quad-word Stores: stfpdx, stfpdux, stfxdx, stfxduxBGP_PU3_FPU_OTHER_STORES_UM3P3 FPU: Other Stores: stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx, stfpsx, stfpsux, stfpiwx, stfsdx, stfsdux, stfssx,stfssux, stfxsx, stfxsuxBGP_PU2_L1_INVALIDATION_UM3P2 L1: Invalidation requestedBGP_PU3_L1_INVALIDATION_UM3P3 L1: Invalidation requestedBGP_COL_A_CH2_VC0_HAVECOL: Arbiter ch2_vc0_haveBGP_COL_A_CH1_VC0_HAVECOL: Arbiter ch1_vc0_haveBGP_COL_A_CH0_VC0_HAVECOL: Arbiter ch0_vc0_haveBGP_COL_A_INJECT_VC0_HAVECOL: Arbiter inj_vc0_haveBGP_COL_A_CH2_VC1_HAVECOL: Arbiter ch2_vc1_haveBGP_COL_A_CH1_VC1_HAVECOL: Arbiter ch1_vc1_haveBGP_COL_A_CH0_VC1_HAVECOL: Arbiter ch0_vc1_haveBGP_COL_A_INJECT_VC1_HAVECOL: Arbiter inj_vc1_haveBGP_COL_AC_GREEDY_MODECOL: Arbiter_core greedy_modeBGP_COL_AC_PENDING_REQUESTS_UM3COL: Arbiter_core requests pendingBGP_COL_AC_WAITING_REQUESTS_UM3COL: Arbiter_core requests waiting (ready to go)BGP_COL_ACLS0_WINSCOL: Arbiter class 0 winsBGP_COL_ACLS1_WINSCOL: Arbiter class 1 winsBGP_COL_ACLS2_WINSCOL: Arbiter class 2 winsBGP_COL_ACLS3_WINSCOL: Arbiter class 3 winsBGP_COL_ACLS4_WINSCOL: Arbiter class 4 winsBGP_COL_ACLS5_WINSCOL: Arbiter class 5 winsBGP_COL_ACLS6_WINSCOL: Arbiter class 6 winsBGP_COL_ACLS7_WINSCOL: Arbiter class 7 winsBGP_COL_ACLS8_WINSCOL: Arbiter class 8 winsBGP_COL_ACLS9_WINSCOL: Arbiter class 9 winsBGP_COL_ACLS10_WINSCOL: Arbiter class 10 winsBGP_COL_ACLS11_WINSCOL: Arbiter class 11 winsBGP_COL_ACLS12_WINSCOL: Arbiter class 12 winsBGP_COL_ACLS13_WINSCOL: Arbiter class 13 winsBGP_COL_ACLS14_WINSCOL: Arbiter class 14 winsBGP_COL_ACLS15_WINSCOL: Arbiter class 15 winsBGP_COL_AS2_BUSYCOL: Arbiter sender 2 busyBGP_COL_AS1_BUSYCOL: Arbiter sender 1 busyBGP_COL_AS1_BUSY_RECEPTIONCOL: Arbiter sender 0 busyBGP_COL_ALC_BUSYCOL: Arbiter local client busy (reception)BGP_COL_AR2_BUSYCOL: Arbiter receiver 2 busyBGP_COL_AR1_BUSYCOL: Arbiter receiver 1 busyBGP_COL_AR0_BUSYCOL: Arbiter receiver 0 busyBGP_COL_ALC_BUSY_INJECTCOL: Arbiter local client busy (injection)BGP_COL_ALU_BUSYCOL: Arbiter ALU busyBGP_COL_AR2_ABORT_UM3COL: Arbiter receiver 2 abortBGP_COL_AR1_ABORT_UM3COL: Arbiter receiver 1 abortBGP_COL_AR0_ABORT_UM3COL: Arbiter receiver 0 abortBGP_COL_ALC_ABORTCOL: Arbiter local client abortBGP_COL_AR2_PACKET_TAKEN_UM3COL: Arbiter receiver 2 packet takenBGP_COL_AR1_PACKET_TAKEN_UM3COL: Arbiter receiver 1 packet takenBGP_COL_AR0_PACKET_TAKEN_UM3COL: Arbiter receiver 0 packet takenBGP_COL_ALC_PACKET_TAKEN_UM3COL: Arbiter local client packet takenBGP_COL_AR0_VC0_DATA_PACKET_RECEIVEDCOL: Receiver 0 vc0 data packet receivedBGP_COL_AR0_VC1_DATA_PACKET_RECEIVEDCOL: Receiver 0 vc1 data packet receivedBGP_COL_AR0_VC1_FULL_UM3COL: Receiver 0 vc1 fullBGP_COL_AR0_HEADER_PARITY_ERROR_UM3COL: Receiver 0 header parity errorBGP_COL_AR1_VC0_DATA_PACKET_RECEIVEDCOL: Receiver 1 vc0 data packet receivedBGP_COL_AR1_VC1_DATA_PACKET_RECEIVEDCOL: Receiver 1 vc1 data packet receivedBGP_COL_AR1_VC0_FULL_UM3COL: Receiver 1 vc0 fullBGP_COL_AR1_VC1_FULL_UM3COL: Receiver 1 vc1 fullBGP_COL_AR2_VC0_DATA_PACKET_RECEIVEDCOL: Receiver 2 vc0 data packet receivedBGP_COL_AR2_VC1_DATA_PACKET_RECEIVEDCOL: Receiver 2 vc1 data packet receivedBGP_COL_AR2_VC0_FULL_UM3COL: Receiver 2 vc0 fullBGP_COL_AR2_VC1_FULL_UM3COL: Receiver 2 vc1 fullBGP_COL_AS0_VC0_EMPTY_UM3COL: Sender 0 vc0 emptyBGP_COL_AS0_VC1_EMPTY_UM3COL: Sender 0 vc1 emptyBGP_COL_AS0_VC0_DATA_PACKETS_SENT_UM3COL: Sender 0 vc0 DATA packets sentBGP_COL_AS0_VC1_DATA_PACKETS_SENT_UM3COL: Sender 0 vc1 DATA packets sentBGP_COL_AS0_RESENDS_UM3COL: Sender 0 resend attemptsBGP_COL_AS1_VC0_EMPTY_UM3COL: Sender 1 vc0 emptyBGP_COL_AS1_VC1_EMPTY_UM3COL: Sender 1 vc1 emptyBGP_COL_AS1_VC0_DATA_PACKETS_SENT_UM3COL: Sender 1 vc0 DATA packets sentBGP_COL_AS1_VC1_DATA_PACKETS_SENT_UM3COL: Sender 1 vc1 DATA packets sentBGP_COL_AS1_RESENDS_UM3COL: Sender 1 resend attemptsBGP_COL_AS2_VC0_EMPTY_UM3COL: Sender 2 vc0 emptyBGP_COL_AS2_VC1_EMPTY_UM3COL: Sender 2 vc1 emptyBGP_COL_AS2_VC0_DATA_PACKETS_SENT_UM3COL: Sender 2 vc0 DATA packets sentBGP_COL_AS2_VC1_DATA_PACKETS_SENT_UM3COL: Sender 2 vc1 DATA packets sentBGP_COL_AS2_RESENDS_UM3COL: Sender 2 resend attemptsBGP_COL_INJECT_VC0_HEADER_ADDEDCOL: Injection vc0 header addedBGP_COL_INJECT_VC1_HEADER_ADDEDCOL: Injection vc1 header addedBGP_COL_RECEPTION_VC0_PACKED_ADDEDCOL: Reception vc0 packet addedBGP_COL_RECEPTION_VC1_PACKED_ADDEDCOL: Reception vc1 packet addedBGP_PU2_SNOOP_PORT0_CACHE_REJECTED_REQUESTP2 SNP: Port 0 snoop cache rejected a requestBGP_PU2_SNOOP_PORT1_CACHE_REJECTED_REQUESTP2 SNP: Port 1 snoop cache rejected a requestBGP_PU2_SNOOP_PORT2_CACHE_REJECTED_REQUESTP2 SNP: Port 2 snoop cache rejected a requestBGP_PU2_SNOOP_PORT3_CACHE_REJECTED_REQUESTP2 SNP: Port 3 snoop cache rejected a requestBGP_PU2_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_ACTIVE_SETP2 SNP: Port 0 request hit a stream register in the active setBGP_PU2_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_ACTIVE_SETP2 SNP: Port 1 request hit a stream register in the active setBGP_PU2_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_ACTIVE_SETP2 SNP: Port 2 request hit a stream register in the active setBGP_PU2_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_ACTIVE_SETP2 SNP: Port 3 request hit a stream register in the active setBGP_PU2_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_HISTORY_SETP2 SNP: Port 0 request hit a stream register in the history setBGP_PU2_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_HISTORY_SETP2 SNP: Port 1 request hit a stream register in the history setBGP_PU2_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_HISTORY_SETP2 SNP: Port 2 request hit a stream register in the history setBGP_PU2_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_HISTORY_SETP2 SNP: Port 3 request hit a stream register in the history setBGP_PU2_SNOOP_PORT0_STREAM_REGISTER_REJECTED_REQUESTP2 SNP: Port 0 stream register rejected a requestBGP_PU2_SNOOP_PORT1_STREAM_REGISTER_REJECTED_REQUESTP2 SNP: Port 1 stream register rejected a requestBGP_PU2_SNOOP_PORT2_STREAM_REGISTER_REJECTED_REQUESTP2 SNP: Port 2 stream register rejected a requestBGP_PU2_SNOOP_PORT3_STREAM_REGISTER_REJECTED_REQUESTP2 SNP: Port 3 stream register rejected a requestBGP_PU2_SNOOP_PORT0_RANGE_FILTER_REJECTED_REQUESTP2 SNP: Port 0 range filter rejected a requestBGP_PU2_SNOOP_PORT1_RANGE_FILTER_REJECTED_REQUESTP2 SNP: Port 1 range filter rejected a requestBGP_PU2_SNOOP_PORT2_RANGE_FILTER_REJECTED_REQUESTP2 SNP: Port 2 range filter rejected a requestBGP_PU2_SNOOP_PORT3_RANGE_FILTER_REJECTED_REQUESTP2 SNP: Port 3 range filter rejected a requestBGP_PU2_SNOOP_PORT0_UPDATED_CACHE_LINEP2 SNP: Port 0 snoop cache updated cache lineBGP_PU2_SNOOP_PORT1_UPDATED_CACHE_LINEP2 SNP: Port 1 snoop cache updated cache lineBGP_PU2_SNOOP_PORT2_UPDATED_CACHE_LINEP2 SNP: Port 2 snoop cache updated cache lineBGP_PU2_SNOOP_PORT3_UPDATED_CACHE_LINEP2 SNP: Port 3 snoop cache updated cache lineBGP_PU2_SNOOP_PORT0_FILTERED_BY_CACHE_AND_REGISTERSP2 SNP: Port 0 snoop filtered by both snoop cache and filter registersBGP_PU2_SNOOP_PORT1_FILTERED_BY_CACHE_AND_REGISTERSP2 SNP: Port 1 snoop filtered by both snoop cache and filter registersBGP_PU2_SNOOP_PORT2_FILTERED_BY_CACHE_AND_REGISTERSP2 SNP: Port 2 snoop filtered by both snoop cache and filter registersBGP_PU2_SNOOP_PORT3_FILTERED_BY_CACHE_AND_REGISTERSP2 SNP: Port 3 snoop filtered by both snoop cache and filter registersBGP_PU3_SNOOP_PORT0_CACHE_REJECTED_REQUESTP3 SNP: Port 0 snoop cache rejected a requestBGP_PU3_SNOOP_PORT1_CACHE_REJECTED_REQUESTP3 SNP: Port 1 snoop cache rejected a requestBGP_PU3_SNOOP_PORT2_CACHE_REJECTED_REQUESTP3 SNP: Port 2 snoop cache rejected a requestBGP_PU3_SNOOP_PORT3_CACHE_REJECTED_REQUESTP3 SNP: Port 3 snoop cache rejected a requestBGP_PU3_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_ACTIVE_SETP3 SNP: Port 0 request hit a stream register in the active setBGP_PU3_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_ACTIVE_SETP3 SNP: Port 1 request hit a stream register in the active setBGP_PU3_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_ACTIVE_SETP3 SNP: Port 2 request hit a stream register in the active setBGP_PU3_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_ACTIVE_SETP3 SNP: Port 3 request hit a stream register in the active setBGP_PU3_SNOOP_PORT0_HIT_STREAM_REGISTER_IN_HISTORY_SETP3 SNP: Port 0 request hit a stream register in the history setBGP_PU3_SNOOP_PORT1_HIT_STREAM_REGISTER_IN_HISTORY_SETP3 SNP: Port 1 request hit a stream register in the history setBGP_PU3_SNOOP_PORT2_HIT_STREAM_REGISTER_IN_HISTORY_SETP3 SNP: Port 2 request hit a stream register in the history setBGP_PU3_SNOOP_PORT3_HIT_STREAM_REGISTER_IN_HISTORY_SETP3 SNP: Port 3 request hit a stream register in the history setBGP_PU3_SNOOP_PORT0_STREAM_REGISTER_REJECTED_REQUESTP3 SNP: Port 0 stream register rejected a requestBGP_PU3_SNOOP_PORT1_STREAM_REGISTER_REJECTED_REQUESTP3 SNP: Port 1 stream register rejected a requestBGP_PU3_SNOOP_PORT2_STREAM_REGISTER_REJECTED_REQUESTP3 SNP: Port 2 stream register rejected a requestBGP_PU3_SNOOP_PORT3_STREAM_REGISTER_REJECTED_REQUESTP3 SNP: Port 3 stream register rejected a requestBGP_PU3_SNOOP_PORT0_RANGE_FILTER_REJECTED_REQUESTP3 SNP: Port 0 range filter rejected a requestBGP_PU3_SNOOP_PORT1_RANGE_FILTER_REJECTED_REQUESTP3 SNP: Port 1 range filter rejected a requestBGP_PU3_SNOOP_PORT2_RANGE_FILTER_REJECTED_REQUESTP3 SNP: Port 2 range filter rejected a requestBGP_PU3_SNOOP_PORT3_RANGE_FILTER_REJECTED_REQUESTP3 SNP: Port 3 range filter rejected a requestBGP_PU3_SNOOP_PORT0_UPDATED_CACHE_LINEP3 SNP: Port 0 snoop cache updated cache lineBGP_PU3_SNOOP_PORT1_UPDATED_CACHE_LINEP3 SNP: Port 1 snoop cache updated cache lineBGP_PU3_SNOOP_PORT2_UPDATED_CACHE_LINEP3 SNP: Port 2 snoop cache updated cache lineBGP_PU3_SNOOP_PORT3_UPDATED_CACHE_LINEP3 SNP: Port 3 snoop cache updated cache lineBGP_PU3_SNOOP_PORT0_FILTERED_BY_CACHE_AND_REGISTERSP3 SNP: Port 0 snoop filtered by both snoop cache and filter registersBGP_PU3_SNOOP_PORT1_FILTERED_BY_CACHE_AND_REGISTERSP3 SNP: Port 1 snoop filtered by both snoop cache and filter registersBGP_PU3_SNOOP_PORT2_FILTERED_BY_CACHE_AND_REGISTERSP3 SNP: Port 2 snoop filtered by both snoop cache and filter registersBGP_PU3_SNOOP_PORT3_FILTERED_BY_CACHE_AND_REGISTERSP3 SNP: Port 3 snoop filtered by both snoop cache and filter registersReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedBGP_MISC_ELAPSED_TIME_UM3MISC: Elapsed running timeGCC: (GNU) 4.1.2 (BGP).symtab.strtab.shstrtab.rela.text.data.bss.rodata.str1.4.sdata.rodata.sbss.comment.note.GNU-stack 4.84  &.l,.p 12.p `@;G;OU^n`   P* 5@M0b`wp  D#D.\C`$PixTLX<$ $@$`P a|o DH Dh t   0 R|jr0` 8/Bx[8T" $%'()@I*@g*H0|,x-0 UPC.cUPC_MutexUPC_SignalsUPC_UserModeUPC_NumberUPC_CounterState_GenNumUPC_StartStop_GenNumUPC_ElapsedTime_HighUPC_ElapsedTime_LowUPC_StartValuesUPC_CountValuesUPC_RankUPC_CoreUPC_NumProcessesUPC_LocationUPC_LockNumUPC_Global_Variables_InitializedUPC_Init_Hardware_CountersUPC_ActiveBGP_UPC_Check_ActiveUPC_AllocateUPC_Check_Event_Id_ValueUPC_DeallocateUPC_Get_CounterIdUPC_Active_EventUPC_Check_Monitored_Event_IdBGP_UPC_Check_Active_EventUPC_Init_Config_InternalUPC_Get_UserModeUPC_Increment_Counter_State_GenNumUPC_Increment_Start_Stop_GenNumUPC_Reset_StateUPC_Try_AllocateUPC_Zero_CtrsUPC_Init_ConfigUPC_Read_CtrprintfUPC_Read_UnitUPC_Check_User_Mode_ValueUPC_Check_Event_Edge_ValueBGP_UPC_Zero_Counter_ValuesBGP_UPC_StartBGP_UPC_Read_Counter_ValueBGP_UPC_Read_CounterBGP_UPC_Initialize_Counter_ConfigUPC_Read_Counter_ValuesstrncpyBGP_UPC_Read_Counter_ValuesBGP_UPC_Read_CountersBGP_UPC_Get_Event_NameBGP_UPC_Get_Event_DescriptionAllocate_UPC_MutexexitputsAllocate_UPC_CounterUPC_Allocate_Global_State_VariablesBGP_UPC_InitializeBGP_UPC_Get_Counter_ModeBGP_UPC_Get_Counter_Threshold_ValueBGP_UPC_Print_Counter_ValueBGP_UPC_Print_Counter_ValuesBGP_UPC_Read_Counter_ConfigBGP_UPC_Monitor_EventBGP_UPC_Set_Counter_ValueBGP_UPC_Set_Counter_Threshold_ValueBGP_UPC_Get_Counter_State_GenNumBGP_UPC_Get_Start_Stop_GenNumBGP_UPC_Print_ConfigBGP_UPC_StopBGP_UPC_Zero_Counter_ValueUPC_DO_NOT_ALLOW_TIME_EVENTSUPC_ALLOW_TIME_EVENTSUPC_NOT_MONITOREDUPC_MONITOREDUPC_SHAREDUPC_EXCLUSIVE\ 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